• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.10a
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• pp.355-358
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• 2009

This paper proposes efficiency optimization control of IPMSM drive using multi hybrid fuzzy controller(HFC). The design of the speed controller based on fuzzy-neural network that is implemented using fuzzy control and neural network. The design of the current based on HFC using model reference and the estimation of the speed based on neural network using ANN controller. In order to maximize the efficiency in such applications, this paper proposes the optimal control method of the armature current. The controllable electrical loss which consists of the copper loss and the iron loss can be minimized by the optimal control of the armature current. The minimization of loss is possible to realize efficiency optimization control for the proposed IPMSM The optimal current can be decided according to the operating speed and the load conditions. This paper considers the design and implementation of novel technique of high performance speed control for IPMSM using multi HFC. Also, this paper proposes speed control of IPMSM using HFC1, current control of HFC2-HFC3 and estimation of speed using ANN controller. The proposed control algorithm is applied to IPMSM drive system controlled HFC, the operating characteristics controlled by efficiency optimization control are examined in detail.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2548-2554
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• 2010

This paper describes a design of fast Fourier transform(FFT) processor for EEG(electroencephalogram) signal analysis for health care services. Hamming window function with 1/2 overlapping is adopted to perform short-time FFT(ST-FFT) of a long period EEG signal occurred in real-time. In order to analyze efficiently EEG signals which have frequency characteristics in the range of 0 Hz to 100 Hz, a 256-point FFT processor is designed, which is based on a single-memory bank architecture and the radix-4 algorithm. The designed FFT processor has been verified by FPGA implementation, and has high accuracy with arithmetic error less than 2%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1565-1571
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• 2010

FMCW(Frequency Modulation Continuous Wave) Radar is very useful for vehicle collision warning system because of the simplicity. In this work, a signal processing part of FMCW vehicle radar system is implemented with flexibility using DSP, FPGA, ADC, and DAC so that the system could adopt lots of algorithm and could be improved through road test. It is shown that the system meets basic requirements as designed, and finds some problems in road test. We briefly discuss the problem which are caused by shadow effect from overlapped target and the distortion of beat frequency from the nonlinearity of VCO and the RCS of vehicle.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.615-618
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• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.841-847
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• 2015

The WAVE(Wireless Access in Vehicular Environments) communication system supports wireless communication environments between vehicles. As the utilization of wireless communication has been increased, attack methods have been varied. There is a high risk on packet manipulations conducted by third party. In this paper, we have designed a secure communication protocol between CA and vehicles. Our designed protocol uses a ECIES(Elliptic Curve Integrated Encryption Scheme) for vehicle authentication and AES(Advanced Encryption Standard) algorithm for protecting packet integrity and confidentiality.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• The Transactions of the Korea Information Processing Society
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• v.7 no.9
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• pp.2867-2875
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• 2000

In this paper, we discuss the implementation of automatic internet text categorization system. A categorization algorithm is designed and the system is implemented by back propagation learning model. Internet documents are collected according to the established categories and tested by Chi-squre ($\chi^2$) for the document leaning, and the category features are extracted. The sets of learning and separating vector are productt>d by these features. As a result of experimental evaluation, we show that this system is more improved in the performance of automatic categorization than the nearest neigbor method.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.1-6
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• 2011

The performance and practicality of cryptosystem for encryption, decryption, and primality test is primarily determined by the implementation efficiency of the modular exponentiation of $a^b$(mod n). To compute $a^b$(mod n), the standard binary squaring still seems to be the best choice. But, the d-ary, (d=2,3,4,5,6) method is more efficient in large b bits. This paper suggests m-numeral system modular exponentiation. This method can be apply to$b{\equiv}0$(mod m), $2{\leq}m{\leq}16$. And, also suggests the another method that is exit the algorithm in the case of the result is 1 or a.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.512-517
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• 2006

In this study, we designed a digital fuzzy logic controller based on FPGA for MPPT of the solar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessors.