• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.129-136
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• 2004

In this paper, we proposed quad variable rates ADPCM coding method for efficient speech transmission and real time porcessing is implemented on TMS320C6711-DSP. The modified ADPCM with four variable coding rates, 16[kbps], 24[kbps], 32[kbps] and 40[kbps] are used for speech window samples for good quality speech transmission at a small data bits and real time encoding and decoding is implemented using DSP. ZCR is used to identify the influence of the noise on the speech signal and to decide the rate change threshold. For noise superior signals, low coding rates are applied to minimize data bit and for noise inferior signals, high coding rates are applied to enhance the speech quality. In most speech telecommunications, silent period takes more than half of the signals, speech quality close to 40[kbps] can be obtained at comparabley low data bits and this is shown by simulation and experiments. TMS320C6711-DSK board has 128K flash memory and performance of 1333MIPS and has meets the requirements for real time implementation of proposed coding algorithm.

• The Journal of the Acoustical Society of Korea
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• v.20 no.6
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• pp.34-39
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• 2001

An adaptive multi-rate (AMR) speech coder was adopted as a standard of W-CDMA by 3GPP and ETSI. The AMR coder is based on the CELP algorithm operating at rates ranging from 12.2 kbps down to 4.75 kbps, and it is a source controlled codec according to the channel error conditions and the traffic loading. In this paper, we implement the DSP S/W of the AMR coder using OakDSPCore. The implementation is based on the CSD17C00A chip developed by C&S Technology, and it is tested using test vectors, for the AMR speech codec, provided by ETSI for the bit exact implementation. The DSP B/W requires 20.6 MIPS for the encoder and 2.7 MIPS for the decoder. Memories required by the Am coder were 21.97 kwords, 6.64 kwords and 15.1 kwords for code, data sections and data ROM, respectively. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.692-704
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• 2005

With the improvement of computer hardware, GPUs(Graphics Processor Units) have tremendous memory bandwidth and computation power. This leads GPUs to use in general purpose computation. Especially, GPU implementation of compute-intensive physics based simulations is actively studied. In the solution of differential equations which are base of physics simulations, tridiagonal matrix systems occur repeatedly by finite-difference approximation. From the point of view of physics based simulations, fast solution of tridiagonal matrix system is important research field. We propose a fast GPU implementation for the solution of tridiagonal matrix systems. In this paper, we implement the cyclic reduction(also known as odd-even reduction) algorithm which is a popular choice for vector processors. We obtained a considerable performance improvement for solving tridiagonal matrix systems over Thomas method and conjugate gradient method. Thomas method is well known as a method for solving tridiagonal matrix systems on CPU and conjugate gradient method has shown good results on GPU. We experimented our proposed method by applying it to heat conduction, advection-diffusion, and shallow water simulations. The results of these simulations have shown a remarkable performance of over 35 frame-per-second on the 1024x1024 grid.

• Journal of Broadcast Engineering
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• v.20 no.4
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• pp.509-520
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• 2015

A design for the merge mode of three dimensional High Efficiency Video Coding (3D-HEVC) is proposed in this paper. The proposed design can reduce the implementation complexity by removing the duplicated modules of the HEVC. For the extension codec, the implementation complexity is as crucial as coding efficiency, meaning if possible, extension codec needs to be easily implemented through by reusing the design of the legacy codec as-is. However, the existing merging process of 3D-HEVC had been built-in integrated in the inside of the HEVC merging process. Thus the duplicated merging process of HEVC had to be fully re-implemented in the 3D-HEVC. Consequently the implementation complexity of the extension codec was very high. The proposed 3D-HEVC merge mode is divided into following two stages; the process to reuse the HEVC modules without any modification; and the reprocessing process for newly added and modified merging modules in 3D-HEVC. By applying the proposed method, the re-implemented HEVC modules, which accounted for 51.4% of 3D-HEVC merge mode confirmed through the operational analysis of algorithm, can be eliminated, while maintaining the same coding efficiency and computational complexity.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.476-482
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• 2012

In this paper, we analyze and compare several co-channel interference mitigation algorithms for WBAN application in 2.4 GHz ISM frequency bands. ML (Maximum Likelihood), OC (Optimal Combining) and MMSE (Minimum Mean Square Error) has been considered for the possible techniques for interference cancellation in view of the trade off between the performance and the complexity of implementation. Based on the channel model of IEEE 802.15.6 standard, simulation results show that ML and OC attains the lower BER performance than that of MMSE if we assume the perfect channel estimation. But, ML and OC have the additional requirement of implementation for his own and other users's channel estimation process, hence, besides the BER performance, the complexity of implementation and the sensitivity to channel estimation error should be considered since it requires the simple and small sized equipment for WBAN system application. In addition, the gap of detection BER performance between ML, OC and MMSE is much decreased under the imperfect channel estimation if we adopt real channel estimation process, therefore, in order to apply to WBAN system, the trade off between the BER performance and complexity of implemetation should be seriously considered to decide the best co-channel interference cancellation for WBAN system application.

• Journal of Advanced Navigation Technology
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• v.25 no.5
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• pp.426-432
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• 2021

Continuous wave (CW) Doppler radar has the advantage of being able to solve the privacy problem unlike camera and obtains signals in a non-contact manner. Therefore, this paper proposes a human activity recognition (HAR) system using CW Doppler radar, and presents the hardware design and implementation results for acceleration. CW Doppler radar measures signals for continuous operation of human. In order to obtain a single motion spectrogram from continuous signals, an algorithm for counting the number of movements is proposed. In addition, in order to minimize the computational complexity and memory usage, binarized neural network (BNN) was used to classify human motions, and the accuracy of 94% was shown. To accelerate the complex operations of BNN, the FPGA-based BNN accelerator was designed and implemented. The proposed HAR system was implemented using 7,673 logics, 12,105 registers, 10,211 combinational ALUTs, and 18.7 Kb of block memory. As a result of performance evaluation, the operation speed was improved by 99.97% compared to the software implementation.

• Journal of information and communication convergence engineering
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• v.1 no.3
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• pp.123-128
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• 2003

This paper has addressed the implementation of the single rate Rate Adaptive Shaper(srRAS) described in RFC2963. This shaper has been proposed to use at the ingress of differentiated services networks providing Assured Forwarding Per Hop Behavior (AFPHB). srRAS is typically used in conjunction with single rate Three Color Marker(srTCM) described in RFC2697. srRAS itself is the tail-drop FIFO that is drained at a variable rate, and srTCM is the marker with metering function. G-srRAS is the same as srRAS except that RAS receives the green token state information from the downstream srTCM to avoid delaying a packet in RAS although there are sufficient tokens available to color the packet green. In this paper, we have addressed the algorithm and the architecture of srRAS, and the scheme to implement srRAS using VHDL(Very high-speed integrated circuit Hardware Description Language) and its related tools.