• KIPS Transactions on Computer and Communication Systems
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• v.2 no.1
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• pp.51-58
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• 2013

This paper describes the design and implementation of the PKI-based EAI system which is used for delivery of sensitive personal information between business systems. For this purpose, we propose a key exchange protocol with some key process : Diffie-Hellman Schema is used to provide forward secrecy, public key-based digital signature is used for EAI Server authentication, data integrity. In addition, in order to minimize the performance impact on the overall EAI systems. The EAI server was designed simply to be used only as a gateway. This paper shows the implementation of Korea public key authentication algorithm standard and a symmetric encryption algorithm for data encryption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11B
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• pp.1020-1029
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• 2008

This paper proposes an high speed pattern matching algorithm and its implementation. The pattern matcher is used to check patterns from realtime input packet. The proposed algorithm can find exact string, range of string values, and combination of string values from input packet at high speed. Given string and rule set are modelled as a state transition graph which can find overlapped strings simultaneously, and the state transition graph is partitioned according to input implicants to reduce implementation complexity. The pattern matcher scheme uses the transformed state transition graph and input packet as an input. The pattern matcher was modelled and implemented in VHDL language. Experimental results show the proprieties of the proposed approach.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.31-38
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• 2010

In tins paper, a new DA(Distributed Arithmetic) tilter implementation technique has been proposed. Contrary to vertical directional calculation of input sample bit format in the conventional DA implementation technique, proposed implementation technique utilizes horizontal directional calculation of input sample bit format. Since proposed technique calculates in horizontal direction, it does not need ROM and utilizes the Modified Booth algorithm. Furthermore proposed technique can be applied to implement the variable coefficients filters in addition to the fixed coefficients filters. Using conventional and proposed techniques, a 20 tap filter is implemented by Verilog-HDL coding. Through Synopsis synthesis tool, it has been shown that 41.6% area reduction can be achieved.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.4
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• pp.53-57
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• 2009

In this paper to computerized patient management of patients applying for a facial recognition algorithm to extract Face Feature Points environment, the implementation of the U-Healthcare offers. First, mobile devices and the pictures and photos of the patient data used as input data, the algorithm AdaBoost Face Feature Points patterns extracted, then stored in an existing database, extracted from the patient's sample photos, matching patterns and makes Face Feature Points. The result is the same patient if the patient information database, in recognizing the disease, doctors, and medical fields to extract the relevant information on the screen to output devices, the patient will present the implementation of recognition system.

• The KIPS Transactions:PartC
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• v.9C no.2
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• pp.163-172
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• 2002

Java Card API porvide benifit for development program based on smart card using limmited resource. This APIs does not support arithmetic operations such as modular arithmetic, greatest common divisor calculation, and generation and certification of prime number, which is necessary arithmetic in PKI algorithm implementation. In this paper, we implement class BigInteger acted in the Java Card platform because that Java Card APIs does not support class BigInteger necessary in implementation of PKI algorithm.

• Journal of IKEEE
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• v.23 no.3
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• pp.978-983
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• 2019

Under the influence of Autonomous Driving and AI, it is important to accurately recognize and judge objects through cameras. In particular, since a method of recognizing an object using a camera can obtain a large amount of information visually compared to other methods, many image signal processing methods have been studied to extract an accurate image. In addition, a lot of research is being carried out to implementation about hardware. In this work, we compare the principles and characteristics of the sorting algorithms that are frequently used in image signal processing and summarize the performance evaluation. Based on this, we define an efficient algorithm when implemented in hardware among efficient sorting algorithms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.12
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Journal of the Korea Society of Computer and Information
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• v.26 no.1
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• pp.11-17
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• 2021

In this paper, we demonstrate a performance boost by parallelizing a purely functional bisimulation algorithm on a multicore processor machine. The key idea of this parallelization is exploiting the referential transparency of purely functional programs to minimize refactoring of the original implementation without any parallel constructs. Both original and parallel implementations are written in Haskell, a purely functional programming language. The change from the original program to the parallel program is minuscule, maintaining almost original structure of the program. Through benchmark, we show that the proposed parallelization doubles the performance of the bisimulation test compared to the original non-parallel implementation. We also shaw that similar performance boost is also possible for a memoized version of the bisimulation implementation.

• Nuclear Engineering and Technology
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• v.55 no.10
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• pp.3898-3906
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• 2023

The paper notes that the most common way of handling spent nuclear fuel (SNF) of power reactors is its temporary long-term dry storage. At the same time, the operation of the dry spent fuel storage facilities almost never use the modern capabilities of information systems in safety control and collecting information for the next studies under implementation of aging management programs. The author proposes a structure of an information system that can be implemented in a dry spent fuel storage facility with ventilated storage containers. To control the thermal component of spent fuel storage safety, a database structure has been developed, which contains 5 tables. An algorithm for monitoring the thermal state of spent fuel was created for the proposed information system, which is based on the comparison of measured and forecast values of the safety criterion, in which the level of heating the ventilation air temperature was chosen. Predictive values of the safety criterion are obtained on the basis of previously published studies. The proposed algorithm is an implementation of the information function of the system. The proposed information system can be used for effective thermal monitoring and collecting information for the next studies under the implementation of aging management programs for spent fuel storage equipment, permanent control of spent fuel storage safety, staff training, etc.