• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1680-1686
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• 1996

The deterministic update method of intensional predicates in a parallel deductive database that deductive database is distributed in a parallel computer architecture in needed. Using updated data from the deterministic update method, a strategy for parallel evaluation of intensional predicates is required. The paper is concerned with an approach to updating parallel deductive database in which very insertion or deletion can be performed in a deterministic way, and an extended parallel semi-naive evaluation algorithm in a parallel computer architecture. After presenting an approach to updating intensional predicates and strategy for parallel evaluation, its implementation is discussed. A parallel deductive database consists of the set of facts being the extensional database and the set of rules being the intensional database. We assume that these sets are distributed in each processor, research how to update intensional predicates and evaluate using the update method. The parallel architecture for the deductive database consists of a set of processors and a message passing network to interconnect these processors.

• Journal of Internet Computing and Services
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• v.9 no.5
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• pp.23-34
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• 2008

The number of web service user is increasing steadily as web-based service is offered in various form. But, web service has a vulnerability such as SQL Injection, Parameter Injection and DoS attack. Therefore, it is required for us to develop Web IDS system and additionally to offer Rule-base intrusion detection/response mechanism against those attacks. However, existing Web IDS system didn't correspond properly on recent web attack mechanism because they didn't including suitable pre-processing procedure on huge web log data. Therfore, we propose an efficient web log pre-processing mechanism for enhancing rule based detection and improving the performance of web IDS base attack response system. Proposed algorithm provides both a field unit parsing and a duplicated string elimination procedure on web log data. And it is also possible for us to construct improved web IDS system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1384-1396
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• 1998

This paper ivestigates the performance of a relative rate (RR) switch algorithm for the rate-based available bit rate (ABR) flow control in asynchronous transfer mode (ATM) networks. A RR switch may notify the network congestion status to the source by suing the congestion indication (CI) bit or no increase (NI)bit in the backward RM (BRM) cells. A RR switch can be differently implemented according to the congestion detectio and notification methods. In this paper, we propose three implementation schemes for the RR switch with different congestion detection and notification methods, and analyze the allowed cell rate (ACR) of a source and the queue length of a switch in steady state. In addition, we derive the upper and lower bounds for the maximum and minimum queue lengths for each scheme respectively, and evaluate the effects of the ABR parameter values on the queue length. Furthermore, we suggest the range of the rage increase factor (RIF) and rate decrease factor (RDF) parameter values which can prevent buffer overflow and underflow at a switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of Korea Multimedia Society
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• v.3 no.3
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• pp.263-271
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• 2000

In this paper, an acoustic echo canceller(AEC) is implemented by ADSP-2181. This AEC uses a noise robust adaptive algorithm and a postprocessing method which attenuates residual echo using cross-correlation between estimated error signal and microphone input signal. We propose new postprocessing method that uses two thresholds to prevent signal distortion after postprocessing and to improve the performance of AEC without extra computational burden. Through experiments using a 16 bit fixed-point DSP board (ADSP-2181 EZ-KIT Lite board), it is shown that the noise robust adaptive algorithm performs well in the double-talk situations and the convergence speed is comparable to NLMS. Using the postprocessor, ERLE is improved about 20 dB. As a result, the AEC with a postprocessor shows better performance than conventional ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.214-227
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• 2003

Developing an application, it is difficult to catch an exact requirement with the conventional text-based method. It has also problems in verification and analysis at each developing stage. Therefore, if an adjustment is required with an error and change of requirement, a bad effect happen in the whole system. In this case, it also affect adversely on the developing cost and period. Meanwhile, if an analysis or verification is performed, the possibility of an error frequency reduces. Thus, not only is it easier to correct the error but also add an new requirement. This thesis embody a TCP/IP congestion control algorithm with SDL which provides automatically graphic interface, verification and analysis to each developing stage. Using SDL gave a clear representation embodiment in each developing stage and easiness of adjustment due to changing requirements or correcting errors. In addition, the stages of protocol have been certified in a simulation by verification of MSC and the results showed a possibility of developing a better TCP/IP protocol.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.800-806
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• 2015

WAVE(Wireless Access in Vehicular Environments) system is wireless communication technology that vehicle sends and receives packets between vehicles or between vehicles and infrastructure in a high-speed mobile environment. In this study, we have designed and implemented a CRL(Certificate Revocation List) download protocol that is used to verify certificate revocation status of the other party when the vehicles communicate with WAVE system. This protocol operates over UDP. And to support security features, also, ECDSA(Elliptic Curve Digital Signature Algorithm) is used for mutual authentication and ECIES(Elliptic Curve Integrated Encryption Scheme) is used to ensure the confidentiality. Moreover, this protocol ensures the integrity of data by adding MAC(Message Authentication Code) to the end of packet and support the error and flow control mechanisms.

• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• The KIPS Transactions:PartD
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• v.9D no.5
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• pp.925-930
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• 2002

This paper discusses techniques for embedding data into 3D polygonal models of geometry. Much researches of Watermarking had been gone as element technology of DRM (digital rights management). But, few research had gone to 3D polygonal model. Most research is limited at text document, 2D image, animation, music etc. RP system is suitable a few production in various goods species, and it is used much in industry to possible reason that produce prototype and find error or incongruent factor at early stage on design in product development childhood. This paper is research about method that insert watermark in STL ( stereolithography) file that have 3D shape model. Proposed algorithm inserts watermark in normal vector region and facet's interior region of 3D shape data. For this reason, 3D shape does not produce some flexure and fulfill invisibility of watermark. Experiment results that insert and extract watermark in normal netter region and facet's Interior region of 3D shape data by proposed algorithm do not influence entirely in 3D shape and show that insertion and extraction of watermark are possible.