• Title/Summary/Keyword: implementation algorithm

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Design of high-speed preamble searcher adequate for RACH preamble structure in WCDMA reverse link receiver (RACH 프리앰블 구조에 적합한 WCDMA 역방향 링크 수신기용 고속 프리앰블 탐색기의 설계)

  • 정은선;도주현;이영용;정성현;최형진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.8A
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    • pp.898-908
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    • 2004
  • In this paper, we propose a high speed preamble searcher feasible for RACH(Random Access Channel) preamble structure in WCDMA reverse link receiver. Unlike IS-95, WCDMA system uses AISMA(Acquisition Indication Sense Multiple Access) process. Because of the time limit between RACH preamble transmission and AI(Acquisition Indicators), and the restriction on the number of RACH signatures assigned to RACH preamble, fast acquisition indication is required for efficient operation. The preamble searcher proposed in this paper is based on 2-antenna system and has adopted FHT algorithm that has the radix-2 16 point FFT structure. The acquisition speed using FHT is 64 times faster than the conventional method that correlates each signature. Based on their fast aquisition scheme, we improved the acquisition performance by calculating the correlation up to the 4096 chips of the total preamble length. The performance is analyzed by using Neyman-pearson method. The proposed algorithm has been applied for the implementation of WCDMA reverse link receiver modem successfully.

Optimisation of multiplet identifier processing on a $PLAYSTATION^{(R)}$ 3 (플레이스테이션 3 상에서 수행되는 멀티플렛 식별자의 최적화)

  • Hattori, Masami;Mizuno, Takashi
    • Geophysics and Geophysical Exploration
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    • v.13 no.1
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    • pp.109-117
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    • 2010
  • To enable high-performance computing (HPC) for applications with large datasets using a $Sony^{(R)}$ $PLAYSTATION^{(R)}$ 3 ($PS3^{TM}$) video game console, we configured a hybrid system consisting of a $Windows^{(R)}$ PC and a $PS3^{TM}$. To validate this system, we implemented the real-time multiplet identifier (RTMI) application, which identifies multiplets of microearthquakes in terms of the similarity of their waveforms. The cross-correlation computation, which is a core algorithm of the RTMI application, was optimised for the $PS3^{TM}$ platform, while the rest of the computation, including data input and output remained on the PC. With this configuration, the core part of the algorithm ran 69 times faster than the original program, accelerating total computation speed more than five times. As a result, the system processed up to 2100 total microseismic events, whereas the original implementation had a limit of 400 events. These results indicate that this system enables high-performance computing for large datasets using the $PS3^{TM}$, as long as data transfer time is negligible compared with computation time.

The Design and Implementation of Two-Way Search Algorithm using Mobile Instant Messenger (모바일 인스턴스 메신저를 이용한 양방향 검색 알고리즘의 설계 및 구현)

  • Lee, Daesik;Jang, Chungryong;Lee, Yongkwon
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.11 no.2
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    • pp.55-66
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    • 2015
  • In this paper, we design and implement a two-way search algorithm that can provide a customized service through the user with real-time two-way communication using a mobile instant messaging service. Therefore, we design and implement the automative search system which enables delivering message to each user mobile terminal from a plurality of relay mobile terminals by utilizing the mobile instant messenger, not to deliver a message from the main server to the mobile instant messenger user directly. Two-way search system using the mobile instant messenger can be immediately collect the user's response is easy to identify the orientation of each user, and thus can be provided to establish a differentiated service plan. Also, It provides a number of services(text, photos, videos, etc) in real-time information to the user by utilizing the mobile instant messenger service without the need to install a separate application. Experiment results, data processing speed of the category processing way to search for the data of the DB server from a user mobile terminal is about 7.06sec, data processing number per minute is about 13 times. The data processing speed of the instruction processing way is about 3.10sec, data processing number per minute is about 10 times. The data processing speed of the natural language processing way is about 5.13sec, per data processing number per minute is about 7 times. Therefore in category processing way, command processing way and natural language processing way, instruction processing way is the most excellent in aspect of data processing speed, otherwise in aspect of per data processing number per minute, the category processing way is the best method.

A Research on Performance Improvement of Wireless LAN System (무선 LAN 시스템 성능개선에 관한 연구)

  • Cho, Juphil
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.5
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    • pp.1028-1033
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    • 2014
  • We investigate the OFDM-based wireless LAN systems operating in the 60 GHz frequency band as part of the fourth-generation (4G) systems. The 60 GHz band is of much interest since this is the band in which a massive amount of spectral space has been allocated worldwide for dense wireless local communications. This paper gives an overview of 60 GHz band channel characteristics and an effect on phase noise. The performance of OFDM system is severely degraded by the local oscillator phase noise, which causes both common phase error and inter-carrier interference. In this paper, we apply phase noise suppression (PNS) algorithm that is easy for implementation to OFDM based 60 GHz wireless LAN system and analyze the SER performance. In case of using the PNS algorithm, SER performance is improved about 6 dB, 7.5 dB, respectively in 16, 64-QAM.

SVC-based Adaptive Video Streaming over Content-Centric Networking

  • Lee, Junghwan;Hwang, Jaehyun;Choi, Nakjung;Yoo, Chuck
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.10
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    • pp.2430-2447
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    • 2013
  • In recent years, HTTP adaptive streaming (HAS) has attracted considerable attention as the state-of-the-art technology for video transport. HAS dynamically adjusts the quality of video streaming according to the network bandwidth and device capability of users. Content-Centric Networking (CCN) has also emerged as a future Internet architecture, which is a novel communication paradigm that integrates content delivery as a native network primitive. These trends have led to the new research issue of harmonizing HAS with the in-network caching provided by CCN routers. Previous research has shown that the performance of HAS can be improved by using the H.264/SVC(scalable video codec) in the in-network caching environments. However, the previous study did not address the misbehavior that causes video freeze when overestimating the available network bandwidth, which is attributable to the high cache hit rate. Thus, we propose a new SVC-based adaptation algorithm that utilizes a drop timer. Our approach aims to stop the downloading of additional enhancement layers that are not cached in the local CCN routers in a timely manner, thereby preventing excessive consumption of the video buffer. We implemented our algorithm in the SVC-HAS client and deployed a testbed that could run Smooth-Streaming, which is one of the most popular HAS solutions, over CCNx, which is the reference implementation of CCN. Our experimental results showed that the proposed scheme (SLA) could avoid video freeze in an effective manner, but without reducing the high hit rate on the CCN routers or affecting the high video quality on the SVC-HAS client.

Design of Multi-Sensor-Based Open Architecture Integrated Navigation System for Localization of UGV

  • Choi, Ji-Hoon;Oh, Sang Heon;Kim, Hyo Seok;Lee, Yong Woo
    • Journal of Positioning, Navigation, and Timing
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    • v.1 no.1
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    • pp.35-43
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    • 2012
  • The UGV is one of the special field robot developed for mine detection, surveillance and transportation. To achieve successfully the missions of the UGV, the accurate and reliable navigation data should be provided. This paper presents design and implementation of multi-sensor-based open architecture integrated navigation for localization of UGV. The presented architecture hierarchically classifies the integrated system into four layers and data communications between layers are based on the distributed object oriented middleware. The navigation manager determines the navigation mode with the QoS information of each navigation sensor and the integrated filter performs the navigation mode-based data fusion in the filtering process. Also, all navigation variables including the filter parameters and QoS of navigation data can be modified in GUI and consequently, the user can operate the integrated navigation system more usefully. The conventional GPS/INS integrated system does not guarantee the long-term reliability of localization when GPS solution is not available by signal blockage and intentional jamming in outdoor environment. The presented integration algorithm, however, based on the adaptive federated filter structure with FDI algorithm can integrate effectively the output of multi-sensor such as 3D LADAR, vision, odometer, magnetic compass and zero velocity to enhance the accuracy of localization result in the case that GPS is unavailable. The field test was carried out with the UGV and the test results show that the presented integrated navigation system can provide more robust and accurate localization performance than the conventional GPS/INS integrated system in outdoor environments.

Material Topology Optimization Design of Structures using SIMP Approach Part I : Initial Design Domain with Topology of Partial Holes (SIMP를 이용한 구조물의 재료 위상 최적설계 Part I : 부분적인 구멍의 위상을 가지는 초기 설계영역)

  • Lee, Dong-Kyu;Park, Sung-Soo;Shin, Soo-Mi
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.20 no.1
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    • pp.9-18
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    • 2007
  • This study shows an implementation of partial holes in an initial design domain in order to improve convergences of topology optimization algorithms. The method is associated with a bubble method as introduced by Eschenauer et al. to overcome slow convergence of boundary-based shape optimization methods. However, contrary to the bubble method, initial holes are only implemented for initializations of optimization algorithm in this approach, and there is no need to consider a characteristic function which defines hole's deposition during every optimization procedure. In addition, solid and void regions within the initial design domain are not fixed but merged or split during optimization Procedures. Since this phenomenon activates finite changes of design parameters without numerically calculating movements and positions of holes, convergences of topology optimization algorithm can be improved. In the present study, material topology optimization designs of Michell-type beam utilizing the initial design domain with initial holes of varied sizes and shapes is carried out by using SIMP like a density distribution method. Numerical examples demonstrate the efficiency and simplicity of the present method.

Hardware Implementation of Elliptic Curve Scalar Multiplier over GF(2n) with Simple Power Analysis Countermeasure (SPA 대응 기법을 적용한 이진체 위의 타원곡선 스칼라곱셈기의 하드웨어 구현)

  • 김현익;정석원;윤중철
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.73-84
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    • 2004
  • This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

A Scheduling Algorithm for Real-Time Traffic in IEEE802.11e HCCA (IEEE 802.11e HCCA 기반의 실시간 트래픽을 위한 스케줄링 알고리즘)

  • Joung, Ji-Noo;Kim, Jong-Jo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.1
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    • pp.1-9
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    • 2010
  • In this paper we propose a scheduling algorithm for supporting Quality of Service(QoS) in IEEE 802.11e HCCA referred to as ASR-DRR and ASD-DRR, which aims at providing improved performance for the support of multimedia traffic. Although We identify the problem of the current IEEE 802.11e HCCA (Hybrid Coordination Function Controlled Channel Access) scheduler and its numerous variations, that the queue information cannot be notified to the Hybrid Coordinator (HC) timely, therefore the uplink delay lengthens unnecessarily. We suggests a simple solution and a couple of implementation practices, namely the Adaptive Scheduler with RTS/CTS (ASR) and Adaptive Scheduler with Data/Ack (ASD). They are both further elaborated to emulate the Deficit Round Robin (DRR) scheduler. They are also compared with existing exemplary schedulers through simulation, and shown to perform well.

Multi-mode Layered LDPC Decoder for IEEE 802.11n (IEEE 802.11n용 다중모드 layered LDPC 복호기)

  • Na, Young-Heon;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.11
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    • pp.18-26
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    • 2011
  • This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.