• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.230-235
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• 2004

This paper describes FPGA implementation of a pointer interpreter which can support a synchronization of SDH(or SONET)-based transmission network. The pointer interpreter consists of a pointer-word extractor and a pointer-word interpreter The pointer-word extractor which is composed of mod-6480 counter, shift register and pointer synchronizing block, finds out the H1 and H2 pointer word from a 51.84 Mb/s AU-3/STS-1 data frame and then performs the synchronizing with a 6.48 Mb/s by dividing them in 8. Based on the extracted pointer word, pointer-word interpreter analyzes pointer states such LOP, AIS and NORM according to pointer state-transition algorithm. It consists of a majority vote, a pointer word valid/invalid check, a pointer justification, and a pointer state check. The simulation results of Xilinx Virtex XCV200PQ240 FPGA chip shows the exact pointer word extraction and correct decision of pointer status based on extracted pointer word. The proposed pointer interpreter is suitable for pointer interpretation of 155 Mb/s STM-1/STS-3 frame.

• Journal of Intelligence and Information Systems
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• v.9 no.3
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• pp.81-97
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• 2003

In this paper, we suggest a method of robust watermarking for protection of multimedia data using the wavelet transform and artificial neural network. for the purpose of implementation, we decompose a original image using wavelet transform at level 3. After we classify transformed coefficients of other subbands using neural network except fur the lowest subband LL$_3$, we apply a calculated threshold about chosen cluster as the biggest. We used binary logo watermarks to make sure that it is true or not on behalf of the Gaussian Random Vector. Besides, we tested a method of dual watermark insertion and extraction. For the purpose of implementation, we decompose a original image using wavelet transform at level 3. After we classify transformed coefficients of other subbands using neural network except for the lowest subband LL$_3$, we apply a above mentioned watermark insert method. In the experimental results, we found that it has a good quality and robust about many attacks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2162-2166
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• 2016

This paper describes the implementation of AUSV system for sonar image acquisition to survey the seabed. The system is controlled by Feed Forward PID algorithm on the vessel for bearing of the thrusters composed of motion sensor and DGPS which calculates the differences between the current location and the destination location for longitude and latitude based on GPS coordinates. As experimental results, the bearing control performance is good that the error distance from the destination positions are under 6m in total survey track of 1km. And the sonar image deviation of a object is under 12 pixels from the manned survey method, which the comparison with the total image quality is almost the same as the manned survey one. Thus the proposed AUSV system is a new method of system can be utilized at the limited survey areas as the surveyor should not be able to approach on sea surface by onboard vessel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1653-1659
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• 2015

Operating Systems is a discipline which handles abstract concepts and techniques. However, most of OS courses have been textbook-oriented theoretical classes. Theoretical classes lead to the decline in the understanding of a lecture and hurt their concentration. Many instructors have tried various ways to help students understand lectures and arouse interests. This paper describes the design and implementation of a web-based educational CPU scheduling simulator which enables learners to set up various situations and simulate scheduling processes using a web browser or a smart-phone. After utilizing the implemented simulator for the class, the survey result for 2014's students shows that it is useful as an educational tool which enhances the understanding of a lecture and develops their problem solving skills.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.3
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• pp.326-331
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• 2010

This paper presents the design and implementation of a data acquisition system with a large number of multi-channels for manufacturing machine. The system having a throughput of 800-ch analog signals has been designed with Quartus II tool and Cyclone II FPGA. The proposed system is suitable for the large scale data handling in order to distinguish whether the operation is correct or not. The designed system is composed of a control unit, voltage divider and USB interface. To reduce the data throughput, we utilized an algorithm which can extract the same data from the achieved data. The test results of the system adapted to a manufacturing machine, show a relevant data acquisition operation of 800 channels in short time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.863-869
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• 2008

In this paper, a system with sensor network security mechanism which can be applied to home network structure is designed and it is implemented on a virtual network of a home network middleware. The basic structure of home networking middleware supports one-to-one (unicast) or broadcast communication mode between the lookup server and service nodes on the network. Confidentiality and authentication are key security factors of the one-to-one communication and user authentication is crucial for broadcasting mode. One of the sensor network's security techniques SPINS consists of SNEP and ${\mu}TESLA$. The SNEP ensures confidentiality and authentication, and ${\mu}TESLA$ provides broadcast authentication. We propose a SPIN based home network middleware and it is implemented by using the CBC-MAC for MAC generation, the counter mode (CTR) for message freshness, the pseudo random function (PRF) and RC5 as encryption algorithm. The implementation result shows that an attacker cannot decrypt the message though he gets the secure key because of CTR mode. In addition, we confirmed that a received message of the server is authenticated using MAC.

• The Journal of the Convergence on Culture Technology
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• v.4 no.4
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• pp.373-377
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• 2018

In this paper, we propose an implementation of a neural network accelerator for reducing the rendering noise using OpenCL. Among the rendering algorithms, we selects a ray tracing to assure a high quality graphics. Ray tracing rendering uses ray to render, less use of the ray will result in noise. Ray used more will produce a higher quality image but will take operation time longer. To reduce operation time whiles using fewer rays, Learning Base Filtering algorithm using neural network was applied. it's not always produce optimize result. In this paper, a new approach to Matrix Multiplication that is based on General Matrix Multiplication for improved performance. The development environment, we used specialized in high speed parallel processing of OpenCL. The proposed architecture was verified using Kintex UltraScale XKU6909T-2FDFG1157C FPGA board. The time it takes to calculate the parameters is about 1.12 times fast than that of Verilog-HDL structure.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.4
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• pp.125-136
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• 2011

The vulnerabilities existed in Korean electricity control systems is unexposed because it is being operated in a closed network with superior security. The threat will become greater once the closed network develops into a smart grid environment with superior intelligence. Security will have a greater impact once each household will be connected to the power plant via the smart meter. This research focuses on stable data transfer in harsh external environment and whole-nation coverage network, and suggested standardized and optimized Virtual Private Network (VPN) Gateway architecture to support Power Line Communication (PLC). The functionality and stability of the prototype has been verified with field tests. For implementation of outdoor type VPN device for smart grid, we adopted PLC low voltage remote-meter-net for data communication. Also, IPSec type tunneling and ARIA algorithm based encryption of data collected by PLC low voltage remote meter is transmitted.