• Title/Summary/Keyword: implementation algorithm

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WCDMA Rreverse Link Beamforming Structure and its Performance Simulation (WCDMA 역방향 빔포밍 구조 및 성능 시뮬레이션)

  • 이재식;박영근;장태규;김재화
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.210-213
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    • 2003
  • This paper presents a beamforming algorithm for the uplink application of a linear array antenna for WCDMA system. A steering beamforming algorithm is designed using a block DFT algorithm and its performance is analyzed and verified using computer simulations. Various environmental parameters such as the number of antenna elements, the number of users, the mobility of the target user, and the status of fast power control are reflected in the simulation study providing themselves as useful design and implementation guides for the reverse link beamforming of WCDMA system.

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H/W Implementation of JPEG compatible fragile watermarking algorithm (JPEG 호환 프래절 워터마킹 알고리즘의 하드웨어 구현)

  • 김진헌;김승원
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.1803-1806
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    • 2003
  • This paper presents a H/W module that executes a fragile watermarking algorithm. The module inputs sequentially quantized DCT values, encodes watermark and then outputs watermarked DCT coefficients. A fragile and invisible watermarking algorithm is adopted, modified and enhanced here to reduce H/W size and image degradation. The module can be directly inserted between DCT quantizer and VLC encoder in wide spread JPEG/MPEG encoder. The module is expected to be used for real-time authentication purpose in DVR(Digital Video Recorder) or digital cameras.

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A Image Alignment Algorithm for an OCR System and its Hardware Implementation (OCR 시스템을 위한 화상 정렬 알고리즘과 고속 하드웨어 구현)

  • 최완수;최진호;정윤구;김수원
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.8
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    • pp.33-40
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    • 1993
  • This paper presents a hardware for image alignment based on proposed new algorithm which can align a small misaligned document image simply by one transformation with a parallel shifting of pixels. This hardware is simulated with VHDL and estimated to be about 65 ms to align an image made up of 380 by 480 pixels. Also, we will demonstrate the effectiveness of the proposed image alignment algorithm in OCR system by comparing its characteristics with those of the existing image rotation algorithms.

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A Study on the Design of an Adder using Carry Propagation Characteristics (자리올림의 전파특성을 이용한 가산회로의 설계에 관한 연구)

  • 이용석;정기현;김용덕
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.5
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    • pp.10-17
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    • 1993
  • This paper suggests a new addition algorithm. A circuit to implement the algorithm and the result of its performance evaluation are presented. The basic idea of the algorithm is that to obtain the sum of two operands, two operands bits are exclusive-ORed and then the result is inverted by the carry from the previous stage. An unique carry prediction method minimizes carry propagation. The proposed circuit has a very simple and regular structure compared with CLA (carry lookahead adder). It also requires less gates for the implementation about 50% and operates faster.

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Distributed/parallel Algorithm Simulator (분산 및 병렬 알고리즘 시뮬레이터)

  • ;R.S.Ramakrishna
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10c
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    • pp.777-779
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    • 1999
  • A new distributed/parallel algorithm simulator, DASim(Distributed Algorithm Simulator), is proposed in this paper. The idea is to ease the task of design, analysis and implementation of distributed algorithms. A small high level language has been proposed for the purpose. Through this non-language specific high level language, the users are spared from the tedious details about how to program distributed or parallel algorithms. Further, visualization of these algorithms are pretty helpful to understand behaviors of these algorithms.

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Application of a Parallel Asynchronous Algorithm to Some Grid Problems on Workstation Clusters

  • Park, Pil-Seong
    • Ocean and Polar Research
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    • v.23 no.2
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    • pp.173-179
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    • 2001
  • Parallel supercomputing is now a must for oceanographic numerical modelers. Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence, the load balancing is a crucial factor, however, it is, in general, difficult to achieve on heterogeneous workstation clusters. We devise an asynchronous algorithm that reduces the idle times of faster processors, and discuss application of the algorithm to some grid problems and implementation on a workstation cluster using Message Passing Interface (MPI).

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A FAST CONSTRUCTION OF GENERALIZED MANDELBROT SETS USING MAIN COMPONENTS WITH EPICYCLOIDAL BOUNDARIES

  • Geum, Young-Hee;Lee, Kang-Sup;Kim, Young-Ik
    • The Pure and Applied Mathematics
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    • v.14 no.3
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    • pp.191-196
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    • 2007
  • The main components in the generalized Mandelbrot sets are under a theoretical investigation for their parametric boundary equations. Using the boundary geometries, a fast construction algorithm is introduced for the generalized Mandelbrot set. This fast algorithm definitely reduces the construction CPU time in comparison with the naive algorithm. Its graphic implementation displays the mysterious and beautiful fractal sets.

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Adaptive Background Subtraction Algorithm with Auto Brightness Control for Consumer-type Cameras

  • Thongkamwitoon T.;Aramvith S.;Chalidabhongse T. H.
    • Journal of Broadcast Engineering
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    • v.10 no.2
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    • pp.156-165
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    • 2005
  • This paper presents a new auto brighoess control algorithm fur adaptive background subtraction. The algorithm is designed to cope with the problem of auto-brightness adjustment feature of consumer-type cameras. The experimental results show the proposed method improves performance of the classification. This will be beneficial to many computer vision applications in term of reducing the cost of implementation and making them more available to the mass consumer market.

Hardware Design of Standard Hash Algorithm HAS-160

  • Youn Choong-Mo;Lee Beom-Geun
    • Journal of information and communication convergence engineering
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    • v.3 no.4
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    • pp.205-208
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    • 2005
  • This paper is about the hardware implementation of the Hash algorithm, HAS-160, which is widely used for Internet security and authentication. VHDL modeling was used for its realization and the operation speed has been increased by the optimized scheduling of the operations required for step operations.

Efficient Path Delay Test Generation for Custom Designs

  • Kang, Sung-Ho;Underwood, Bill;Law, Wai-On;Konuk, Haluk
    • ETRI Journal
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    • v.23 no.3
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    • pp.138-149
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    • 2001
  • Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

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