• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.3
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• pp.133-141
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• 2002

Most maximum power point tracking(MPPT) control algorithm is based on Perturb and Observe(P&O) and Incremental Conductance(IncCond). In comparison with P&O and IncCond algorithm, the dynamic and tracking characteristic of IncCond algorithm is better than P&O algorithm in condition of rapidly changing solar radiation. But in the case of digital implementation, the InCond algorithm has error en decision of maximum power operation point(MPOP). To solve this problem, this paper proposes a improved IncCond algorithm, which can determine the MPOP correctly by inserting the test signal in control input. This paper proposes a novel MPPT control algorithm for the digitally implemented photovoltaic system in condition of rapidly changing solar radiation. To verify the validity of the proposed control algorithm. the computer simulation and experiment are carried out.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.3
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• pp.158-164
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• 2003

This paper proposes a percentage current differential relaying algorithm for bus protection using an advanced compensating algorithm of the secondary current of current transformers (CTs). The compensating algorithm estimates the core flux at the start of the first saturation based on the value of the second-difference of the secondary current. Then, it calculates the core flux and compensates distorted currents using the magnetization curve. The algorithm Is unaffected by a remanent flux. The simulation results indicate that the proposed algorithm can discriminate internal faults from external faults when the CT saturates. This paper concludes by implementing the algorithm into a TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory. The proposed algorithm can improve not only stability of the relay in the case of an external fault but sensitivity of the relay in the case of an internal fault.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3135-3137
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• 1999

We propose two robust blind equalization algorithms based on multi-stage clustering blind equalization algorithm, which are called a complex classification update algorithm(CCUA) and an error compensation algorithm(ECA). The first algorithm is a tap-updating algorithm which each computes classified real and imaginary parts in order to reduce computations and the complexity of implementation as a stage increase. The second one is a algorithm which can achieve faster convergence speed because error of equalizer input make always fixed. Test results confirm that the proposed algorithms with faster convergence and lower complexity outperforms both constant modulus algorithm (CMA) and conventional multi-stage blind clustering algorithm(MSA) in reducing the SER as well as the MSE at the equalizer output.

• Journal of Digital Contents Society
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• v.18 no.6
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• pp.1151-1156
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• 2017

It is common to achieve lower performance in traversing tree data structures in GPU than one expects. In this paper, we analyze the reason of lower-than-expected performance in GPU tree traversal and present that the warp divergences is caused by the branch instructions ("if${\ldots}$ else") which appear commonly in tree traversal CUDA codes. Also, we compare the parallel shifted sort algorithm which can reduce the number of warp divergences with a kd-tree CUDA implementation to show that the shifted sort algorithm can work faster than the kd-tree CUDA implementation thanks to less warp divergences. As the analysis result, the shifted sort algorithm worked about 16-fold faster than the kd-tree CUDA implementation for $2^{23}$ query points and $2^{23}$ data points in $R^3$ space. The performance gaps tend to increase in proportion to the number of query points and data points.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.128-135
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• 2004

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1095-1102
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• 2016

In this paper, we propose a decoding scheme that can apply to a three dimensional turbo product code(TPC) with a single parity check code(SPC). In general, SPC is used an axis with shortest code length in order to maximize a code rate of the TPC. However, SPC does not have any error correcting capability, therefore, the error correcting capability of the three-dimensional TPC results in little improvement in comparison with the two-dimensional TPC. We propose two schemes to improve performance of three dimensional TPC decoder. One is $min^*$-sum algorithm that has advantages for low complexity implementation compared to Chase-Pyndiah algorithm. The other is a modified serial iterative decoding scheme for high performance. In addition, the simulation results for the proposed scheme are shown and compared with the conventional scheme. Finally, we introduce some practical considerations for hardware implementation.

• Journal of IKEEE
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• v.23 no.1
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• pp.207-213
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• 2019

In this paper, we propose a low-complexity feature detection algorithm for object tracking and present hardware architecture design and implementation results for real-time processing. The existing Shi-Tomasi algorithm shows good performance in object tracking applications, but has a high computational complexity. Therefore, we propose an efficient feature detection algorithm, which can reduce the operational complexity with the similar performance to Shi-Tomasi algorithm, and present its real-time implementation results. The proposed feature detector was implemented with 1,307 logic slices, 5 DSP 48s and 86.91Kbits memory with FPGA. In addition, it can support the real-time processing of 54fps at an operating frequency of 114MHz for $1920{\times}1080FHD$ images.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.253-256
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• 2000

This paper describes a DSP implementation of a real-time 3D sound localization algorithm with the use of a low power embedded DSP. A distinctive feature of this implementation is that the audible frequency band is divided into three, in accordance with the sound reflection and diffraction phenomena through different media from a certain sound source to human ears, and then in each subband a specific implementation procedure of the 3D sound localization is devised so as to operate real-time at a low frequency of 50MHz on a 16bit fixed-point DSP. Thus out DSP implementation can provide a listener with 3D sound effects through a headphone at low cost and low power consumption.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.57-60
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• 2000

This paper presents a new adaptive fast motion estimation algorithm along with its architecture. The conventional algorithm such as full - search algorithm, three step algorithm have some disadvantages which are related to the amount of computation, the quality of image and the implementation of hardware, the proposed algorithm uses spatial correlation and a slope of motion vector in order to reduce the amount of computation and preserve good image quality, The proposed algorithm is better than the conventional Block Matching Algorithm(BMA) with regard to the amount of computation and image quality. Also, we propose an efficient at chitecture to implement the proposed algorithm. It is suitable for real time processing application.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.9
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• pp.2153-2161
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• 1993

Self-tuning control algorithms for an input-amplitude constrained system are developed and implemented. Magnitude of control input for small motors is generally restricted to narrow bound due to actuator saturation. The gain-adjusted control algorithm and the bounded-gain control algorithm proposed in this study yield smoother control input variations within the magnitude constraints comparing with the existing Clarke's suboptimal control algorithm. In the gain-adjusted control algorithm, the feedforward gain is adjusted using maximum gain, while in the bounded-gain control algorithm, the feedforward gain is bounded using weighting factor. For the DC servo motor control, the system performances of the proposed algorithms are compared with those of the existing algorithm by computer simulation and experiment. It is shown that the input variations of the proposed algorithms are smoother as compared with the existing algorithm.