• Korean Journal of Cognitive Science
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• v.18 no.4
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• pp.457-483
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• 2007

Database Semantics (DBS) attempts to provide a comprehensive and integrated approach to human communication which seeks theory-implementation transparency. Two key components of DBS are Word bank as a data structure and left-Associative Grammar (LAG) as an algorithm. This study aims to provide a pilot implementation of Korean in DBS. First, it is shown how the three separate modules of grammar in DBS, namely, Hear, Think, and Speak, combine to form an integrated system that simulates a cognitive agent by making use of a simple Korean sentence as an example. Second, we provide a detailed analysis of the structure in Korean that is a characteristic of Korean involving numerals, classifiers, and nouns, thereby illustrating how DBS can be applied to Korean. We also discuss an issue raised in the literature concerning a problem that arises when we try to apply the LAG algorithm to the analysis of head-final language like Korean, and then discuss some possible solution to the problem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.962-970
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• 2004

This paper presents an efficient implementation of the 2.4 kbps EHSX(Enhanced Harmonic Stochastic Excitation) speech coder on a TMS320C6701$^{TM}$ floating-point digital signal processor. The EHSX speech codec is based on a harmonic and CELP(Code Excited Linear Prediction) modeling of the excitation signal respectively according to the frame characteristic such as a voiced speech and an unvoiced speech. In this paper, we represent the optimization methods to reduce the complexity for real-time implementation. The complexity in the filtering of a CELP algorithm that is the main part for the EHSX algorithm complexity can be reduced by converting program using floating-point variable to program using fixed-point variable. We also present the efficient optimization methods including the code allocation considering a DSP architecture and the low complexity algorithm of harmonic/pitch search in encoder part. Finally, we obtained the subjective quality of MOS 3.28 from speech quality test using the PESQ(perceptual evaluation of speech quality), ITU-T Recommendation P.862 and could get a goal of realtime operation of the EHSX codec.c.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1133-1138
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• 2018

Lightweight Encryption Algorithm (LEA) is one of the most promising lightweight block cipher algorithm due to its high efficiency and security level. There are many works on the efficient LEA implementation. However, many works missed the secure application services where the IoT platforms perform secure communications between heterogeneous IoT platforms. In order to establish the secure communication channel between them, the encryption should be performed in the on-the-fly method. In this paper, we present the LEA implementation performing the on-the-fly method over the ARM Cortex-M3 processors. The general purpose registers are fully utilized to retain the required variables for the key scheduling and encryption operations and the rotation operation is optimized away by using the barrel-shifter technique. Since the on-the-fly method does not store the round keys, the RAM requirements are minimized. The implementation is evaluated over the ARM Cortex-M3 processor and it only requires 34 cycles/byte.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.4
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• pp.625-634
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• 2006

In this paper, an efficient and fast algorithm to reduce calculation amount of FIR(Finite Impulse Responses) filtering is proposed. Proposed algorithm enables arbitrary size of parallel processing, and their structures are also easily derived. Furthermore, it is shown that the number of multiplication/sample is remarkably reduced. For theoretical improvement, numbers of sub filters are compared with those of conventional algorithm. In addition to the theoretical improvement, it is shown that number of element for hardwired implementation are reduced comparison to those of the conventional algorithm.

• Journal of Information Technology Applications and Management
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• v.12 no.1
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• pp.49-68
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• 2005

It is one of the crucial components of electronic logistics systems to manage logistics information of cargos and transportation companies and to mediate appropriate brokerage between them. Due to the advance of e-Commerce technologies many kinds of logistics transactions can be handled by means of EDI or XML/EDI applications. but the brokering processing relies mostly on the traditional processes and the research in this field is still at the initial stage. In this paper we study a logistics brokering system for ships and cargos and describe the design and implementation of the system. We analyze the brokering constraints for logistics of cargos and ships and construct an optimization model for their brokering. We also suggest a brokering procedure and a simple heuristic algorithm with respect to the proposed matching criteria. The experimental result shows that the proposed greedy-based heuristic algorithm performs very well. In its response time the proposed algorithm executed within a couple of seconds independently of the number of cargos and the container capacities of ships. The output of the algorithm is very close to that of the optimal solution. showing higher than 95% of approximation. The proposed system is implemented for the Web environment using JSP and PL/SQL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.423-436
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• 2003

Submarine optical fiber cable construction consists of marine survey, PLGR(Pre Lay Grapnel Run), shore-end-work, laying order. PLGR is the work process which removes the oceanic contaminations(ropes, wires, nets etc.) in the route before laying the submarine optical cable. This PLGR is work to ease the cable lay safely in seabed, improve the performance of Plough and ROV((Remotely-Operated Vehicle) laying work, and protect laying equipment. This paper presents the optimization algorithm implementation of KP(Kilometer Post) and XTE(Cross Track Error) to manage marine survey and PLGR work efficiently. In this paper, we composes overall PLGR work, and proposed optimization algorithm of KP and XTE. For the validity evaluation of this paper, KP and XTE decision algorithm are implemented and tested.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.490-500
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• 1996

The conventional method to deal with current transformer (CT) Saturation is over dimensioning of the core so that CTs can carry up to 20 times the rated current without exceeding 10% ratio correction. However, this not only reduces the sensitivity of relays as some errors may still be present in the secondary current when a severe fault occurs, but also increases the CT size. This paper presents an algorithm for compensating the distorted secondary current of iron-cored CTs under CT saturation using the magnetization (flux-current : .lambda.-i) curve and its performance is examined for fault currents encountered on a typical 345[kV] Korean transmission system, under a variety of different system and fault conditions. In addition, the results of hardware implementation of the algorithm using a TMS320C10 digital signal processor are also presented. The proposed algorithm can improve the sensitivity of relays to low level internal faults, maximize the stability of relays for external faults, and reduce the required CT core cross-section significantly. (author). refs., figs.

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.56-60
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• 2017

This paper describes the design and implementation of fall-down detection algorithm based on image processing. The fall-down detection algorithm separates objects by using background subtraction and binarization after grayscale conversion of the input image acquired by the camera, and recognizes the human body by using labeling operation. The recognized human body can be monitored on the display image, and an alarm is generated when fall-down is detected. By using computer simulation, the proposed algorithm has shown a detection rate of 90%. We verify the feasibility of the proposed system by verifying the function by using the prototype test implemented on the DSP image processing board.