• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Smart Media Journal
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• v.6 no.3
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• pp.9-14
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• 2017

This paper is a study on the hardware implementation of the encryption and decryption block of the lightweight block cipher algorithm LEA which can be used for tiny devices in IoT environment. It accepts all secret keys with 128 bit, 192 bit, and 256 bit sizes and aims at the integrated implementation of encryption and decryption functions. It describes design results of applying pipeline method for performance enhancement. When a decryption function is executed, round keys are used in reverse order of encryption function. An efficient hardware implementation method for minimizing performance degradation are suggested. Considering the number of rounds are 24, 28, or 32 times according to the size of secret keys, pipeline of LEA is implemented so that 4 round function operations are executed in each pipeline stage.

• International journal of advanced smart convergence
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• v.9 no.4
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• pp.62-73
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• 2020

In this paper, we present electronic acupuncture needles we have developed using intelligence technology based on Bluetooth in order to allow anyone to simply receive customized remote diagnosis and treatment by clicking on the menu of the smartphone regardless of time and place. In order to determine the health condition and disease of patients, we have developed a software and a hardware of electronic acupuncture needles, operating on Bluetooth which transmits biometric data to oriental medical doctors using the functions of automatically determining pulse diagnosis, tongue diagnosis, and oxygen saturation; the functions are most commonly used in herbal treatment. In addition, using fuzzy logic and reasoning based on smartphones, we present in this paper an algorithm and the results of completion of hardware implementation for electronic acupuncture needles, appropriate for the body conditions of patients; the algorithm and the hardware implementation are for a treatment time duration by electronic acupuncture needles, an automatic determinations of pulse diagnosis, tongue diagnosis, and oxygen saturation, a function implementation for automatic display of acupuncture point, and a strength adjustment of electronic acupuncture needles. As a result of our simulation, we have shown that the treatment of patients, performed using an Electronic Acupuncture Needles based on intelligence, is more efficient compared to the treatment that was performed before.

• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.264-271
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• 2021

From an information security perspective, protecting sensitive data requires utilizing algorithms which resist theoretical attacks. However, treating an algorithm in a purely mathematical fashion or in other words abstracting away from its physical (hardware or software) implementation opens the door to various real-world security threats. In the modern age of electronics, cryptanalysis attempts to reveal secret information based on cryptosystem physical properties, rather than exploiting the theoretical weaknesses in the implemented cryptographic algorithm. The correlation power attack (CPA) is a Side-Channel Analysis attack used to reveal sensitive information based on the power leakages of a device. In this paper, we present a power Hacking technique to demonstrate how a power analysis can be exploited to reveal the secret information in AES crypto-core. In the proposed case study, we explain the main techniques that can break the security of the considered crypto-core by using CPA attack. Using two cryptographic devices, FPGA and 8051 microcontrollers, the experimental attack procedure shows that the AES hardware implementation has better resistance against power attack compared to the software one. On the other hand, we remark that the efficiency of CPA attack depends statistically on the implementation and the power model used for the power prediction.

• International Journal of Computer Science & Network Security
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• v.22 no.7
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• pp.75-84
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• 2022

The efficiency of the regional fiscal policy implementation is based on the achievement of target criteria in the formation and distribution of own financial resources of local budgets, reducing their deficit and reducing dependence on transfers. It is also relevant to compare the development of financial autonomy of regions in the course of decentralisation of fiscal relations. The study consists in the cluster analysis of the effectiveness of fiscal policy implementation in the context of 24 regions and the capital city of Kyiv (except for temporarily occupied territories) under conditions of fiscal decentralisation. Clustering of the regions of Ukraine by 18 indicators of fiscal policy implementation efficiency was carried out using Ward's minimum variance method and k-means clustering algorithm. As a result, the regions of Ukraine are grouped into 5 homogeneous clusters. For each cluster measures were developed to increase own revenues and minimize dependence on official transfers to increase the level of financial autonomy of the regions. It has been proved that clustering algorithms are an effective tool in assessing the effectiveness of fiscal policy implementation at the regional level and stimulating further expansion of financial decentralisation of regions.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.220-223
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• 1999

Conventional double DES has been not only shown to have a vulnerable drawback to attack method called 'Meet-in-the-Middle', but also to be hard to use that it is because software implementation has a number of problem in real time processing. This paper describes the design and implementation of modified Isolated double DES algorithm using VHDL for resolving the above problems. In this approach, we also discuss an efficient method for increasing cipher strength through expansion of key length.

• Journal of the Chungcheong Mathematical Society
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• v.15 no.2
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• pp.97-107
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• 2003

An efficient algorithm for the multiplication in a binary finite filed using a normal basis representation of $F_{2^m}$ is discussed and proposed for software implementation of elliptic curve cryptography. The algorithm is developed by using the storage scheme of sparse matrices.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.10 no.15
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• pp.51-58
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• 1987

This paper describes a new variant of Successive Linear Programming (SLP) algorithm called PSLP (Penalty SLP, 1985) using the multiplicative formulation Proposed by Beale (1978). A Fortran computer implementation md its performance are also summarized.

• Journal of the Korea Society for Simulation
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• v.9 no.2
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• pp.15-25
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• 2000

Since data security problems are very important in the information age, cryptographic algorithms for encryption and decryption have been studied for a long time. The GOST(Gosudarstvennyi Standard or Government Standard) algorithm as a data encryption algorithm with a 256-bit key is a 64-bit block algorithm developed in the former Soviet Union. In this paper, we describe how to design an encryption chip based on the GOST algorithm. In addition, the GOST algorithm is compared with the DES(Data Encryption Standard) algorithm, which has been used as a conventional data encryption algorithm, in modeling techniques and their performance. The GOST algorithm whose key size is relatively longer than that of the DES algorithm has been expanded to get better performance, modeled in VHDL, and simulated for implementation with an CPLD chip.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.44-49
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• 2003

This paper describes a percentage current differential relaying algorithm for bus protection blocked by a CT saturation detection algorithm. The detection algorithm blocks the output of a current differential relay only if a differential current is caused by CT saturation in the case of an external fault. Moreover, if a current differential relay operates faster than the detection algorithm, the blocking signal is not ignited. On the other hand. if the detection algorithm operates faster than a current differential relay, the output of the relay is blocked. The results of the simulation show that the proposed algorithm can discriminate internal faults from external faults ever when a CT is saturated in both cases. This paper concludes by implementing the algorithm into the TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory The algorithm can not only increase the sensitivity of the current differential relay but Improve the stability of the relay for an external faults.