• Journal of the Korea Convergence Society
• /
• v.10 no.8
• /
• pp.21-26
• /
• 2019

This paper proposes a fatigue recognition method using the C4.5 algorithm. Based on domestic and international studies on fatigue evaluation, we have completed the fatigue self - assessment scale in combination with lifestyle and cultural characteristics of Chinese people. The scales used in the text were applied to 58 sub items and were used to assess the type and extent of fatigue. These items fall into four categories that measure physical fatigue, mental fatigue, personal habits, and fatigue outcomes. The purpose of this study is to analyze the leading causes of fatigue formation and to recognize the degree of fatigue, thereby increasing the personal interest in fatigue and reducing the risk of cerebrovascular disease due to excessive fatigue. The recognition rate of the fatigue recognition system using the C4.5 algorithm was 85% on average, confirming the usefulness of this proposal.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.16 no.4
• /
• pp.689-698
• /
• 2021

In this paper, lane recognition, steering control and speed control algorithms were developed using Bluetooth wireless communication and image processing techniques. Instead of recognizing road traffic signals based on image processing techniques, a methodology for recognizing the permissible road speed by receiving speed codes from electronic traffic signals using Bluetooth wireless communication was developed. In addition, a steering control algorithm based on PWM control that tracks the lanes using the Canny algorithm and Hough transform was developed. A vehicle prototype and a driving test track were developed to prove the accuracy of the developed algorithm. Raspberry Pi and Arduino were applied as main control devices for steering control and speed control, respectively. Also, Python and OpenCV were used as implementation languages. The effectiveness of the proposed methodology was confirmed by demonstrating effectiveness in the lane tracking and driving control evaluation experiments using a vehicle prototypes and a test track.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.31 no.6
• /
• pp.1149-1156
• /
• 2021

The Grover algorithm, which accelerates the brute force attack, is applicable to key recovery of symmetric key cryptography, and NIST uses the Grover attack cost for symmetric key cryptography to estimate the post-quantum security strength. In this paper, we estimate the attack cost of Grover's algorithm by implementing DES as a quantum circuit. NIST estimates the post-quantum security strength based on the attack cost of AES for symmetric key cryptography using 128, 192, and 256-bit keys. The estimated attack cost for DES can be analyzed to see how resistant DES is to attacks from quantum computers. Currently, since there is no post-quantum security index for symmetric key ciphers using 64-bit keys, the Grover attack cost for DES using 64-bit keys estimated in this paper can be used as a standard. ProjectQ, a quantum programming tool, was used to analyze the suitability and attack cost of the quantum circuit implementation of the proposed DES.

• The Journal of the Convergence on Culture Technology
• /
• v.8 no.5
• /
• pp.613-618
• /
• 2022

Research on artificial intelligence based on SNN (Spiking Neural Networks) is drawing attention as a next-generation artificial intelligence that can overcome the limitations of artificial intelligence based on DNN (Deep Neural Networks) that is currently popular. In this paper, we describe the structure of the SNN compiler, a system SW that generate code from SNN description for neuromorphic computing systems. We also introduce the algorithms used for compiler implementation and present experimental results on how the execution time varies in neuromorphic computing systems depending on the the mapping algorithm. The mapping algorithm proposed in the text showed a performance improvement of up to 3.96 times over a random mapping. The results of this study will allow SNNs to be applied in various neuromorphic hardware.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.5
• /
• pp.547-555
• /
• 2008

This parer proposed the path mismatch detection and compensation algorithm with closed form for linear amplification with non-linear components(LINC) system implementation. The LINC system has a merit of using the high efficient amplifier by transferring the non-constant envelop signal which is high peak to average signal ratio into constant envelop signal. However, the performance degradation is very sensitive to the path mismatch such as an amplitude mismatch and a phase mismatch. In order to improve the path mismatch, the error detection and compensation method is introduced by the use of four test signals. Since the presented method has the closed form solution, the efficient and fast detection is available. The digital-IF structure of LINC system applied by the proposed error detection and compensation algorithm was implemented. The performance was evaluated with the IEEE 802.16 WiMAX baseband sinal which has 7 MHz channel bandwidth and 16-QAM. The Error Vector Magnitude(EVM) of -37.37 dB was obtained through performance test, which meets performance requirement of -24 dB EVM. As a result, the introduced error detection and compensation method was verified to improve the LINC system performance.

• Journal of the Institute of Convergence Signal Processing
• /
• v.15 no.2
• /
• pp.48-54
• /
• 2014

For the element ${\alpha}{\in}GF(p^n)$, two kinds of bases are known. One is a conventional polynomial basis of the form $\{1,{\alpha},{\alpha}^2,{\cdots},{\alpha}^{n-1}\}$, and the other is a normal basis of the form $\{{\alpha},{\alpha}^p,{\alpha}^{p^2},{\cdots},{\alpha}^{p^{n-1}}\}$. In this paper we consider the method of generating normal bases which construct the finite field $GF(p^n)$, as an n-dimensional extension of the finite field GF(p). And we analyze the code sequence generating algorithm and derive the implementation functions of code sequence generator based on the normal bases. We find the normal polynomials of degrees, n=5 and n=7, which can generate normal bases respectively, design, and construct the code sequence generators based on these normal bases. Finally, we produce two code sequence groups(n=5, n=7) by using Simulink, and analyze the characteristics of the autocorrelation function, $R_{i,i}(\tau)$, and crosscorrelation function, $R_{i,j}(\tau)$, $i{\neq}j$ between two different code sequences. Based on these results, we confirm that the analysis of generating algorithms and the design and implementation of the code sequence generators based on normal bases are correct.

• 전자공학회논문지 IE
• /
• v.45 no.4
• /
• pp.11-18
• /
• 2008

This study is implementation of attitude control system(ACS - Attitude Control System). for a multi legs robot. This study designs H/W of Inertial Measurement Unit (IMU) and attitude control algorithm S/W. Compare performance with Mtx and MTx in order to verify action performance of this system after implementation, and will verify a system integrated IMU of a multi-legs robot. ACS uses Gyro and an accelerometer and an earth magnetism sensor, and it is a system controlling a roll, pitch angle attitude of an object. Generally, low price MEMS is difficult to calculate a correct situation of an object as an error occurs severely the Inertial sensor. This study implements IMU in order to develop ACS as use MEMS, accelerometer, Gyro sensor and earth magnetism sensor. Design algorithm each a roll, pitch, yaw attitude guaranteeing regular performance, and do poling in a system as include an attitude calculation program in an IMU system implemented. Mixed output of Gyro and an accelerometer, and recompensed a roll, pitch angle, and loaded in this study on a target platform in order to implement the ACS which guaranteed performance more than a continuously regular level, and operated by real time, and did porting, and verified.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.131-137
• /
• 2013

The barrel distortion makes serious problems in a wide-angle camera employing a lens of a short focal length. This paper presents a low-complexity hardware architecture for a real-time barrel distortion corrector and its implementation. In the proposed barrel distortion corrector, the conventional algorithm is modified so that the correction is performed incrementally, which results in the reduction of the number of required hardware modules for the distortion correction. The proposed barrel distortion corrector has a pipelined architecture so as to achieve a high-throughput correction. The correction rate is 74.86 frames per sec at the operating frequency of 314MHz in a $0.11{\mu}m$ CMOS process, where the frame size is $2048{\times}2048$. The proposed barrel distortion corrector is implemented with 14.3K logic gates.

• Journal of the Korea Convergence Society
• /
• v.11 no.6
• /
• pp.43-49
• /
• 2020

In spite of the notable advancements of millimeter wave communication technologies, the 60 GHz Wi-Fi is still not widespread yet, mainly due to the high limitation of coverage. Conventionally, it has been hardly possible to support a high data rate with fast beam adaptation while keeping atmospheric beamforming coverage. To solve these challenges in the 60 GHz communication system, holistic system designs are considered. we implemented an enhanced design LDPC decoder enabling 6.72 Gbps coded-throughput with minimal implementation loss, and our proposed phase-tracking algorithm guarantees 3.2 dB performance gain at 1 % PER in the case of 16 QAM modulation and LDPC code-rate 3/4.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.12
• /
• pp.1079-1085
• /
• 2013

Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple $2^M$ decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation.