• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.123-129
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• 1997

This study is implementation of transmitter signal processing of MF/HF DSC Controller, obliligation system of GMDSS, focused on the technique of processing to encode the distress and general signal of the DSC message. We analyzed recommendation which prescribed frequencies, operational procedures and technical sequence of the DSC and suggested the basic circuit to be materialize the function of a distress alert and general calf of the DSC equipment using Microprocessor, constructed the algorithm of processing a message, programmed it using C language.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.377-381
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• 1999

This paper presents a implementation of digital motion control system for induction motor vector drives using the 16bit DSP TMS320F240. The DSP controller enable enhanced real time algorithm and cost-effective design of intelligent controllers for induction motors which can be yield enhanced operation, fewer system components, lower system cost, increased efficiency and high performance. The system presented are speed and current sensing, sine look-up table and generated SVPWM by fully integrated control software. The developed system in a implementation are shown a good speed response characteristic results and high performance features. The system can be adapted variform motor drive system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2452-2462
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• 2000

Network games can be regarded as a kind of group work to make target results through competition and cooperation. This paper summarizes the requirements for a group communication platform to support multi-user network games and describes the design and implementation principles of such a dead reckoning, This approach enhances the productivity of network game development by separating the development phase of a game from making it networked. Under the this paper, flexible enough to provide multimedia games networked by various forms of architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.9
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• pp.883-892
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• 1991

In this thesis explanation of new knapsack algorithm for public key system difficulty test and parallel architecture for implementation are suggested. Past Merkle-Hellman’s knapsack is weak in Shamir or Brickell`s attack by the effects of mapping into other easy sequenoes. But linearly shift knapsack system compensates them.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.488-493
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• 1989

In this paper, the structure of CMAC address mapping is first revisited, and the address hashing function and the random mapping is discussed in the conventional CMAC implementation. Then the effective size of CMAC memory is derived from the modulus property of the CMAC address vector, and a new hashing function for the effective memory mapping is proposed for a CMAC implementation with feasible memory size and no troublesome random mapping. Finally, the performance of the conventional CMAC learning algorithm and that of the proposed new CMAC scheme arc compared via simulations.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.2
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• pp.47-54
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• 1986

Hardware implementation of a 32-channel MFC digital receiver has not been easy and simple, because it requires real time processing of PCM data. In this paper, we introduce a method of designing an MFC digital receiver compactly by the channel distribution method. We have implemented the MFC digital receiver to process many cnannels by distributing channels of the TDM input data directly to the commercial digital signal processor chips(NEC uPD7720), and by carrying out the modified Goertzel Algorithm. The design of low cost, reliable, high speed, and compact MFC receiver will be shown.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2350-2352
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• 2004

This paper presents the implementation-tation of the real-time software GPS Receiver based on FFT and FLL assisted PLL tracking algorithm. The FFT(fast fourier transform) based GPS si-gnal acquisition scheme provides a fast TTFF(time to first fix) performance. The tracking based on FLL assisted PLL enables tracking of GPS signal in a high dynamic environment. The designed software GPS receiver uses the indexing method for generating replica carrier to reduce computation load. The performance of the implemented GPS receiver is evaluated using high-dynamic simulated data from a simulator and real static data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

• Journal of applied mathematics & informatics
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• v.4 no.1
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• pp.1-16
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• 1997

In this paper we study efficient parallel implementation for hybrid iterative methods BICGSTAB and BICGSTAB $(\ell)$ with ${Well}=2$ on the CRAY C90 and the efficiency of their parallel performance is evaluated. numerical experiments suggest that on the CRAY C90 a parallel inner product algorithm called PDOTB be used for the par-allelization of hybrid iterative methods containing sensitive values of inner products. Lastly it is shown that the number of iterations in which parallel hybrid iterative methods satisfy a certain convergence criterion depends on the number of processors to be used.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.255-260
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• 2001

This paper presents a new approach to the design of neural control system using digital signal processors in order to improve the precision and robustness. Robotic manipulators have become increasingly important in the field of flexible automation. High speed and high-precision trajectory tracking are indispensable capabilities for their versatile application. The need to meet demanding control requirement in increasingly complex dynamical control systems under significant uncertainties, leads toward design of intelligent manipulation robots. The TMS320C31 is used in implementing real time neural control to provide an enhanced motion control for robotic manipulators. In this control scheme, the networks introduced are neural nets with dynamic neurons, whose dynamics are distributed over all the network nodes. The nets are trained by the distributed dynamic back propagation algorithm. The proposed neural network control scheme is simple in structure, fast in computation, and suitable for implementation of real-time control. Performance of the neural controller is illustrated by simulation and experimental results for a SCARA robot.