• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• Journal of Wind Energy
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• v.14 no.4
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• pp.87-97
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• 2023

Due to the limitations of onshore wind power, the wind power industry is currently transitioning to offshore wind power. There has been active research on the development of a floating LiDAR system (FLS) that is easy to install at a low cost. The Carbon Trust published a commercialization roadmap for FLS in 2013, and an updated version was released in 2018, taking into account industry experience. The roadmap divides the development maturity of FLS into three stages: Stage 1 (prototype), Stage 2 (pre-commercialization), and Stage 3 (commercialization), each of which requires availability and accuracy assessment. The results must meet the requirements of the Key Performance Index (KPI) for each stage. Therefore, when developing FLS, the motion compensation algorithm of the FLS is essential because the LiDAR can produce incorrect measurements of wind speed and direction due to the six degrees of freedom in motion. In this study, we implemented the FLS motion compensation algorithm developed by Nassif, F.B. et al. and validated it using data provided by Fraunhofer. In conclusion, the results showed that the determination coefficients of wind speed and wind direction were improved compared to those obtained from the met mast.

• Journal of Digital Contents Society
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• v.18 no.4
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• pp.739-745
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• 2017

This paper presents and discusses an implementation of the GPU shifted sorting method to find approximate k nearest neighbors which executes within "warp", the minimum execution unit in GPU parallel architecture. Also, this paper presents the comparison results with other two common nearest neighbor searching methods, GPU-based kd-tree and ANN (Approximate Nearest Neighbor) library. The proposed implementation focuses on the cases when k is small, i.e. 2, 4, 8, and 16, which are handled efficiently within warp to consider it is very common for applications to handle small k's. Also, this paper discusses optimization ways to implementation by improving memory management in a loop for the CUB open library and adopting CUDA commands which are supported by GPU hardware. The proposed implementation shows more than 16-fold speed-up against GPU-based other methods in the tests, implying that the improvement would become higher for more larger input data.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.7-14
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• 2013

As mobiles devices with high-spec camera built in are used widely, the visual quality enhancement of the high-resolution images turns out to be one of the key capabilities of the mobile devices. Due to the limited computational resources of the mobile devices and the size of the high-resolution images, we should choose an image processing algorithm not too complex and use an efficient implementation technology. One of the simple and widely used image quality enhancement algorithms is contrast stretching. Java libraries running on a virtual machine, JNI (Java Native Interface) based native C/C++, and NEONTM SIMD (Single Instruction Multiple Data) are common implementation technologies in the case of Android smartphones. Using these three implementation technologies, we have implemented two image contrast stretching algorithms - linear and equalized, and compared the computation times. The native C/C++ and the NEONTM SIMD outperformed the native C/C++ implementation by 56-78 and 50-76 time faster respectively.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.215-226
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• 2016

Modeling, control and implementation of a real redundant robot with five Degrees Freedom (DOF) of the SCARA (Selective Compliant Assembly Robot Arm) manipulator type is presented. Through geometric methods and structural and functional considerations, the inverse kinematics for redundant robot can be obtained. By means of a modification of the classical sliding mode control law through a hyperbolic function, we get a new algorithm which enables reducing the chattering effect of the real actuators, which together with the learning and adaptive controllers, is applied to the model and to the real robot. A simulation environment including the actuator dynamics is elaborated. A 5 DOF robot, a communication interface and a signal conditioning circuit are designed and implemented for feedback. Three control laws are executed in: a simulation structure (together with the dynamic model of the SCARA type redundant manipulator and the actuator dynamics) and a real redundant manipulator of the SCARA type carried out using MatLab/Simulink programming tools. The results, obtained through simulation and implementation, were represented by comparative curves and RMS indices of the joint errors, and they showed that the redundant manipulator, both in the simulation and the implementation, followed the test trajectory with less pronounced maximum errors using the adaptive controller than the other controllers, with more homogeneous motions of the manipulator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.56-64
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• 1998

Multi-layered perceptrons that are a nonlinear neural network model, have been widely used for various applications mainly thanks to good function approximation capability for nonlinear fuctions. However, for digital hardware implementation of the multi-layere perceptrons, the quantization scheme using "look-up tables (LUTs)" is commonly employed to handle nonlinear signmoid activation functions in the neworks, and thus requires large amount of storage to prevent unacceptable quantization errors. This paper is concerned with a new effective methodology for digital hardware implementation of multi-layered perceptrons, and proposes a "piecewise affine approximation" method in which input domain is divided into (small number of) sub-intervals and nonlinear sigmoid function is linearly approximated within each sub-interval. Using the proposed method, we develop an expression and an error backpropagation type learning algorithm for a multi-layered perceptron, and compare the performance with the quantization method through Monte Carlo simulations on XOR problems. Simulation results show that, in terms of learning convergece, the proposed method with a small number of sub-intervals significantly outperforms the quantization method with a very large storage requirement. We expect from these results that the proposed method can be utilized in digital system implementation to significantly reduce the storage requirement, quantization error, and learning time of the quantization method.quantization method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.404-406
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• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.11
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• pp.972-981
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• 2013

Future aspects of the has turned into a network centric warfare(NCW). Organically combined wired and wireless networks in a variety of cross-of-the-art combat power factor utilization of information and communication technology is a key element of NCW implementation. At used various information in the NCW must be the confidentiality and integrity excellent then quick situation assessment through reliability the real-time processing, which is the core of winning the war. In this paper, NCW is one of the key technologies of the implementation of 128-bit output stream cipher algorithm is proposed. AES-based stream cipher developed by applying modified OFB mode the confidentiality and integrity as well as hardware implementation to the security and real-time processing is superior.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.10 no.2
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• pp.38-47
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• 2001

In this paper, a new scheme of adaptive-neuro control system is presented to implement real-time control of robot manipulator using Digital Signal Processors. Digital signal processors, DSPs, are micro-processors that are particularly developed for fast numerical computations involving sums and products of measured variables, thus it can be programmed and executed through DSPs. In addition, DSPs are as fast in computation as most 32-bit micro-processors and yet at a fraction of therir prices. These features make DSPs a viable computational tool in digital implementation of sophisticated controllers. Unlike the well-established theory for the adaptive control of linear systems, there exists relatively little general theory for the adaptive control of nonlinear systems. Adaptive control technique is essential for providing a stable and robust perfor-mance for application of robot control. The proposed neuro control algorithm is one of learning a model based error back-propagation scheme using Lyapunov stability analysis method.The proposed adaptive-neuro control scheme is illustrated to be a efficient control scheme for the implementation of real-time control of robot system by the simulation and experi-ment.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.2
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• pp.81-88
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• 2014

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.