• Title/Summary/Keyword: implementation algorithm

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A Study on Implementation of 4D and 5D Support Algorithm Using BIM Attribute Information - Focused on Process Simulation and Quantity Calculation - (BIM 속성정보를 활용한 4D, 5D 설계 지원 알고리즘 구현 및 검증에 관한 연구 - 공정시뮬레이션과 물량산출을 중심으로 -)

  • Jeong, Jae-Won;Seo, Ji-Hyo;Park, Hye-Jin;Choo, Seung-Yeon
    • Journal of the Regional Association of Architectural Institute of Korea
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    • v.21 no.4
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    • pp.15-26
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    • 2019
  • In recent years, researchers are increasingly trying to use BIM-based 3D models for BIM nD design such as 4D (3D + Time) and 5D (4D + Cost). However, there are still many problems in efficiently using process management based on the BIM information created at each design stage. Therefore, this study proposes a method to automate 4D and 5D design support in each design stage by using BIM-based Dynamo algorithm. To do this, I implemented an algorithm that can automatically input the process information needed for 4D and 5D by using Revit's Add-in program, Dynamo. In order to support the 4D design, the algorithm was created to enable automatic process simulation by synchronizing process simulation information (Excel file) through the Navisworks program, BIM software. The algorithm was created to automatically enable process simulation. And to support the 5D design, the algorithm was developed to enable automatic extraction of the information needed for mass production from the BIM model by utilizing the dynamo algorithm. Therefore, in order to verify the 4D and 5D design support algorithms, we verified the applicability through consultation with related workers and experts. As a result, it has been demonstrated that it is possible to manage information about process information and to quickly extract information from design and design changes. In addition, BIM data can be used to manage and input the necessary process information in 4D and 5D, which is advantageous for shortening construction time and cost. This study will make it easy to improve design quality and manage design information, and will be the foundation for future building automation research.

A ENA algorithm for Performance Enhancement of Satellite Link using TCP (TCP를 사용하는 위성링크에서의 성능 향상을 위한 ENA 알고리즘)

  • 이정규;김상희
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.8A
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    • pp.1177-1185
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    • 2000
  • In this paper, We report on the performance issues faced by TCP based applications on satellite link having long propagation delay and high probability of bit erros and propose ENA(Error Notification Ack) algorithm for TCP Performance Enhancement. TCP Protocol cannot distinguish errored segments(in noisy medium) from losses of genuine network congestion and react as if there is network congestion. Therefore, Slow Start and Congestion avoidance mechanism are initiated. It happen this case in satellite link. Therefore it reduce the transmission rate and drop the performance. So, in this paper We propose ENA algorithm which is distinguished errored segments from losses of network congestion. And We propose the method of algorithm's implementation. And We evaluate the Performance of Tahoe, Reno, Sack TCP with ENA. As results, TCP Performance is better.

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Performance Analysis and Efficient Decoding Algorithm for Space-Time Turbo codes (시공간 turbo 부호의 성능 분석과 효율적인 복호 알고리즘)

  • Shin Na na;Lee Chang woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.4C
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    • pp.191-199
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    • 2005
  • Space-time turbo codes have been studied extensively as a powerful and bandwidth efficient error correction code over the wireless communication environment. In this paper, the efficient algorithm for decoding space-time turbo codes is proposed. The proposed method reduces the computational complexity by approximating a prior information for a iterative decoder. The performance of space-time turbo codes is also analyzed by using the fixed point implementation and the efficient method for approximating the Log-MAP algorithm is proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

Design and Implementation of effective ECC Encryption Algorithm for Voice Data (음성 데이터 보안을 위한 효율적인 ECC 암호 알고리즘 설계 및 구현)

  • Kim, Hyun-Soo;Park, Seok-Cheon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2374-2380
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    • 2011
  • Many people is preferred to mVoIP which offers call telephone-quality and convenient UI as well as free of charge. On the other hand, security of mVoIP is becoming an issue as it using Internet network may have danger about wiretapping. Although traditionally encryption algorithm of symmetric key for security of voice data has been used, ECC algorithm of public key type has been preferring for encryption because it is stronger in part the strength of encryption than others. However, the existing way is restricted by lots of operations in poor mobile environment. Thus this paper proposes the efficiency of resource consumption way by reducing cryptographic operations.

An FPGA Implementation of High-Speed Flexible 27-Mbps 8-StateTurbo Decoder

  • Choi, Duk-Gun;Kim, Min-Hyuk;Jeong, Jin-Hee;Jung, Ji-Won;Bae, Jong-Tae;Choi, Seok-Soon;Yun, Young
    • ETRI Journal
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    • v.29 no.3
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    • pp.363-370
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    • 2007
  • In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half-rate turbo decoder designed for binary quadrature phase-shift keying (B/QPSK) modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implement the proposed scheme on a field-programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.

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Forward kinematic analysis of a 6-DOF parallel manipulator using genetic algorithm (유전 알고리즘을 이용한 6자유도 병렬형 매니퓰레이터의 순기구학 해석)

  • 박민규;이민철;고석조
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.1624-1627
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    • 1997
  • The 6-DOF parallel manipulator is a closed-kindmatic chain robot manipulator that is capable of providing high structural rigidity and positional accuracy. Because of its advantage, the parallel manipulator have been widely used in many engineering applications such as vehicle/flight driving simulators, rogot maniplators, attachment tool of machining centers, etc. However, the kinematic analysis for the implementation of a real-time controller has some problem because of the lack of an efficient lagorithm for solving its highly nonliner forward kinematic equation, which provides the translational and orientational attitudes of the moveable upper platform from the lenght of manipulator linkages. Generally, Newton-Raphson method has been widely sued to solve the forward kinematic problem but the effectiveness of this methodology depend on how to set initial values. This paper proposes a hybrid method using genetic algorithm(GA) and Newton-Raphson method to solve forward kinematics. That is, the initial values of forward kinematics solution are determined by adopting genetic algorithm which can search grobally optimal solutions. Since determining this values, the determined values are used in Newton-Raphson method for real time calcuation.

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Design of Efficient Flicker Detector for CMOS Image Sensor (CMOS Image sensor 를 위한 효과적인 플리커 검출기 설계)

  • Lee, Pyeong-Woo;Lee, Jeong-Guk;Kim, Chae-Sung
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.739-742
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    • 2005
  • In this paper, an efficient detection algorithm for the flicker, which is caused by mismatching between light frequency and exposure time at CMOS image sensor (CIS), is proposed. The flicker detection can be implemented by specific hardware or complex signal processing logic. However it is difficult to implement on single chip image sensor, which has pixel, CDS, ADC, and ISP on a die, because of limited die area. Thus for the flicker detection, the simple algorithm and high accuracy should be achieved on single chip image sensor,. To satisfy these purposes, the proposed algorithm organizes only simple operation, which calculates the subtraction of horizontal luminance mean between continuous two frames. This algorithm was verified with MATLAB and Xilinx FPGA, and it is implemented with Magnachip 0.18 standard cell library. As a result, the accuracy is 95% in average on FPGA emulation and the consumed gate count is about 7,500 gates (@40MHz) for implementation using Magnachip 0.18 process.

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Efficient Design and Performance Analysis of a Hardware Right-shift Binary Modular Inversion Algorithm in GF(p)

  • Choi, Piljoo;Lee, Mun-Kyu;Kong, Jeong-Taek;Kim, Dong Kyue
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.425-437
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    • 2017
  • For efficient hardware (HW) implementation of elliptic curve cryptography (ECC), various sub-modules for the underlying finite field operations should be implemented efficiently. Among these sub-modules, modular inversion (MI) requires the most computation; therefore, its performance might be a dominant factor of the overall performance of an ECC module. To determine the most efficient MI algorithm for an HW ECC module, we implement various classes of MI algorithms and analyze their performance. In contrast to the common belief in previous research, our results show that the right-shift binary inversion (RS) algorithm performs well when implemented in hardware. In addition, we present optimization methods to reduce the area overhead and improve the speed of the RS algorithm. By applying these methods, we propose a new RS-variant that is both fast and compact. The proposed MI module is more than twice as fast as the other two classes of MI: shifting Euclidean (SE) and left-shift binary inversion (LS) algorithms. It consumes only 15% more area and even 5% less area than SE and LS, respectively. Finally, we show that how our new method can be applied to optimize an HW ECC module.

Implementation of Class-Based Low Latency Fair Queueing (CBLLFQ) Packet Scheduling Algorithm for HSDPA Core Network

  • Ahmed, Sohail;Asim, Malik Muhammad;Mehmood, Nadeem Qaisar;Ali, Mubashir;Shahzaad, Babar
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.2
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    • pp.473-494
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    • 2020
  • To provide a guaranteed Quality of Service (QoS) to real-time traffic in High-Speed Downlink Packet Access (HSDPA) core network, we proposed an enhanced mechanism. For an enhanced QoS, a Class-Based Low Latency Fair Queueing (CBLLFQ) packet scheduling algorithm is introduced in this work. Packet classification, metering, queuing, and scheduling using differentiated services (DiffServ) environment was the points in focus. To classify different types of real-time voice and multimedia traffic, the QoS provisioning mechanisms use different DiffServ code points (DSCP).The proposed algorithm is based on traffic classes which efficiently require the guarantee of services and specified level of fairness. In CBLLFQ, a mapping criterion and an efficient queuing mechanism for voice, video and other traffic in separate queues are used. It is proved, that the algorithm enhances the throughput and fairness along with a reduction in the delay and packet loss factors for smooth and worst traffic conditions. The results calculated through simulation show that the proposed calculations meet the QoS prerequisites efficiently.

A Study on a Compensation of Decoded Video Quality and an Enhancement of Encoding Speed

  • Sir, Jaechul;Yoon, Sungkyu;Lim, Younghwan
    • Journal of the Korea Computer Graphics Society
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    • v.6 no.3
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    • pp.35-40
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    • 2000
  • There are two problems in H.26X compression technique. One is compressing time in encoding process and the other is degradation of the decoded video quality due to high compression rate. For transferring moving pictures in real-time, it is required to adopt massively high compression. In this case, there are a lot of losses of an original video data and that results in degradation of quality. Especially degradation called by blocking artifact may be produced. The blocking artifact effect is produced by DCT-based coding techniques because they operate without considering correlation between pixels in block boundaries. So it represents discontinuity between adjacent blocks. This paper describes methods of quality compensation for H.26x decoded data and enhancing encoding speed for real-time operation. Our goal of the quality compensation is not to make the decoded video identical to a original video but to make it perceived better through human eyes. We suggest an algorithm that reduces block artifact and clears decoded video in decoder. To enhance encoding speed, we adopt new four-step search algorithm. As shown in the experimental result, the quality compensation provides better video quality because of reducing blocking artifact. And then new four-step search algorithm with $MMX^{TM}$ implementation improves encoding speed from 2.5 fps to 17 fps.

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