• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.39-45
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• 1997

This study presents the first experimental data for the impact of hot-carrier degradtion on the performance of CMOS folded-cascode op-amps. A folded-cascode op-amp which has an NMOS input pair has been designed and fabricated using a 0.8.mu.m single-poly, double-metal CMOS process. After high voltage stress, the degradtion of perfomrance parameters such as open-metal CMOS process. After high voltage stress, the degradation of performance parameters such as open-loop voltage gain, unity-gain frequency and phase margin has been analized and physically explaniend in terms of hot carrier degradation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.129-135
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• 1996

In this paper, the hot carrier effect and device degradation of deep submicrometer SC-PMOSFETs have been measured and characterized. It has been shown that the substrate current of a 0.15$\mu$m PMOSFET increases with increasing of impact ionization rate, and the impact ionization rate is a function of the gate length and gate bias voltage. Correlation between gate current and substrate current is investigated within the general framework of the lucky-electron. It is found that the impact ionization rate increases, but the device degradation is not serious with decreasing effective channel length. SCIHE is suggested as the possible phusical mechanism for enhanced impact ionization rate and gate current reduction. Considering the hot carrier induced device degradation, it has been found that the maximum supply voltage is about -2.6V for 0.15$\mu$m PMOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.53-58
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• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

• 전자공학회논문지 IE
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• v.45 no.2
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• pp.1-5
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• 2008

In this work, RF performance degradation due to hot carrier effects in SOI MOSFET have been measured and analyzed. The LNA that designed at $V_{GS}=0.8V$, f=2.5GHz, gain is 16.51dB and noise figure is 1.195dB. After stress at SOI, the LNA's gain and noise figure change of 15.3dB and 1.44dB with before stress.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.469-472
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• 1987

The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.109-111
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• 2007

In this paper, MOS devices with ultrathin gate dielectrics (5.5 nm) are characterized and compared with those with conventional oxides particularly for nanoscale CMOS applications. Nitrogen concentrations and profiles in the nitride gate dielectrics were obtained that will play an important role in improving both hot-carrier lifetime and resistance to boron penetration. This approach seems very useful for future nanoscale CMOS device applications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.