• Journal of the Korean Society for Precision Engineering
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• v.10 no.3
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• pp.182-190
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• 1993

In manufacturing process of semiconductor package, the thermal stress owing to high temperature in moulding and the bubbles generated in chip bonding process become main causes to produce void. On this study we evaluated quantitatively void size by use of ultrasonic spectroscopy method which analyze the reflective pulses with broad band frequency in frequency domain, and after destructive testing we verified effectiv- eness of sizing void by use of ultasonic spectroscopy.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1462-1465
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• 1996

This paper evaluated dielectic characteristics on EPR, Polyester and insulation of these different interface. Dielectric characteristics of insulation rubber, Polyester increace greatly according as temperature increases have no effect on applied voltage and pressure. On the condition that interface exists, we confirmed that dielectric characteristics had been influence on semiconductor which had high $tan{\delta}$.

• 전기의세계
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• v.21 no.1
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• pp.17-21
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• 1972

Electrical resistivity and switching phenomena in glass semiconductor of AsTe and AsTeGa is studied. Samples sliced from ingot which is air quenched or water quenched, show high resistivity at room temperature. The resistivity of the AsTe and AsTeGa is 1*10$^{6}$ .ohm.-cm and 5*10$^{6}$ .ohm.-cm at 27.deg. C. Switching phenomena take place in thin the thick samples. Holding voltage is different with the thickness of the samples and the characteristics of switching in the thin and thick samhles are similar. When square wave pulse voltage is applied, delay time is detected to 5.mu.sec by oscilloscpoe.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.857-859
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• 1999

본 연구에서는 Poly-Si TFT-LCD 패널에 내장할 수 있는 새로운 방식의 디지털 데이터 구동회로를 설계하였는데, 제안된 데이터 구동회로의 특징 및 장점을 요약하면 다음과 같다. 첫째, 단순한 구조의 샘플드램프 D/A Conversion 회로로 구성되어 회로가 복잡하지 않고, 소요되는 TFT의 수가 적으며, 패널의 스캔방식(Inversion Method : Row/Column/Dot)을 쉽게 선택할 수 있다. 둘째, 기존의 디지털 데이터 구동회로와는 달리, D/A Conversion을 위해 필요한 기준 전압원의 수가적어 입력 핀 수를 적게 가져갈 수 있다. 셋째, Ramp 신호의 조정에 의해 감마 보정 등을 포함한 데이터의 에러에 대한 보정이 수월하다. 넷째, 라인 스친 방식으로 구동하므로 기존의 샘플 앤 홀드방식의 아날로그 구동회로에 비해 화소 데이터의 시간적 안정성을 충분히 확보할 수 있다.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.377-377
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• 2014

We demonstrate the high temperature-dependent electrical behavior at 2D multilayer MoS2 transistor. Our previous reports explain that the extracted field-effect mobility of good device was inversely proportional to the increase of temperature. Because scattering mechanism is dominated by phonon scattering at a well-designed MoS2 transistor, having, low Schottky barrier. However, mobility at an immature our $MoS_2$ transistor (${\mu}m$ < $10cm^2V^{-1}s^{-1}$) is proportional to the increase temperature. The existence of a big Schottky barrier at $MoS_2-Ti$ junction can reduce carrier transport and lead to lower transistor conductance. At high temperature (380K), the field-effect mobility of multilayer $MoS_2$ transistor increases from 8.93 to $16.9cm^2V^{-1}sec^{-1}$, which is 2 times higher than the value at room temperature. These results demonstrate that carrier transport at an immature $MoS_2$ with a high Schottky barrier is mainly affected by thermionic emission over the energy barrier at high temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.40-40
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• 2008

$InGaZnO_4$ based thin film transistors (TFTs) are of interest for large area and low cost electronics. The TFTs have strong potential for application in flat panel displays and portable electronics due to their high field effect mobility, high on/off current ratios, and high optical transparency. The application of such room temperature processed transistors, however, is often limited by the operation voltage and long-tenn stability. Therefore, attaining an optimum thickness is necessary. We investigated the thickness dependence of a room temperature grown $MgO_{0.3}BST_{0.7}$ composite gate dielectric and an $InGaZnO_4$ (IGZO) active semiconductor on the electrical characteristics of thin film transistors fabricated on a polyethylene terephthalate (PET) substrate. The TFT characteristics were changed markedly with variation of the gate dielectric and semiconductor thickness. The optimum gate dielectric and active semiconductor thickness were 300 nm and 30 nm, respectively. The TFT showed low operating voltage of less than 4 V, field effect mobility of 21.34 cm2/$V{\cdot}s$, an on/off ratio of $8.27\times10^6$, threshold voltage of 2.2 V, and a subthreshold swing of 0.42 V/dec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.5
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• pp.282-285
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• 2014

We have investigated the structural and electrical properties of Si-Zn-Sn-O (SZTO) thin films deposited by RF magnetron sputtering at various deposition temperatures from RT to $350^{\circ}C$. All the SZTO thin fims are amorphous structure. The mobility of SZTO thin film has been changed depending on the deposition temperature. SZTO thin film transistor shows mobility of 8.715 $cm^2/Vs$ at room temperature. We performed the electrical stress test by applying gate and drain voltage. SZTO thin film transistor shows good stability deposited at room temperature while showing poor stability deposited at $350^{\circ}C$. As a result, the electrical performance and stability have been changed depending on deposition temperature mainly because high deposition temperature loosened the amorphous structure generating more oxygen vacancies.

• Journal of the Semiconductor & Display Technology
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• v.5 no.3 s.16
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• pp.29-32
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• 2006

Because of new requirements related to the employment of SMT(Surface Mounting Technology) manufacturing and the diversity of components on high density PCB(Printed Circuit Boards), Thermal control of the reflow process is required in order to achieve acceptable yields and reliability of SMT assemblies. Accurate control of the temperature distribution during the reflow process is one of the major requirements, especially in lead-free assembly. This study has been performed for reflow process using the commercial CFD(Computational Fluid Dynamics) tool for predicting flow and temperature distributions. Porous plate was installed to prevent leakage flow which was one of the major problem of temperature uniformity in the reflow process. There is a separation region where the flow is turned. Outside wall made of porous plate is to prevent and minimize separation region for acquiring uniform temperature during operation. This paper provided design concept from CFD results of the steady state temperature distribution and flow field inside a reflow oven.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.95-99
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• 2011

$(1-x)BaTiO_3+(x)Cd_5(PO_4)_3Cl$ ceramics were prepared by the conventional ceramic technique, i.e., solid state reaction at high temperature. The concentration of $Cd_5(PO_4)_3C$ was varied from 0.01 to 0.15 mole fraction. In order to study the phase transitions of our ceramics, the Raman scattering spectra were measured as functions of concentration x and temperature. It was found that the soluble limit of $Cd_5(PO_4)_3Cl$ in $BaTiO_3$ was the x=0.05 composition and $BaTiO_3$ phase disappeared above x=0.10. A new phase identified as $Ba_4Ti_3P_2O_{15}$ was detected in all samples of our compositions. The Curie temperature shifts up to $130^{\circ}C$ as the concentration x increases from zero to 0.05 and shift down to $95^{\circ}C$ as further increases to 0.08. For the increase of the Curie temperature, it is suggested that it can result from the inhibition of displacement of $Ti^{4+}$ in the distorted octahedron due to well dispersed $Ba_4Ti_3P_2O_{15}$ and $Cd_5(PO_4)_3Cl$ phase.