• Journal of Communications and Networks
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• v.14 no.3
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• pp.273-279
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• 2012

In this paper, we propose an iterative interstream interference cancellation technique for system with frequency selective multiple-input multiple-output (MIMO) channel. Our method is inspired by the fact that the cancellation of the interstream interference can be regarded as a reduction in the magnitude of the interfering channel. We show that, as iteration goes on, the channel experienced by the equalizer gets close to the single input multiple output (SIMO) channel and, therefore, the proposed SIMO-like equalizer achieves improved equalization performance in terms of normalized mean square error. From simulations on downlink communications of $2{\times}2$ MIMO systems in high speed packet access universal mobile telecommunications system standard, we show that the proposed method provides substantial performance gain over the conventional receiver algorithms.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.169-177
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• 2016

To realize high-speed intrusion detection by accommodating many regular expression (regex)-based signatures and growing network link capacities, we propose the Service TimE-Aware Load-balancing (STEAL) algorithm. This work is motivated from the observation that utilization of a many-core network intrusion detection system (NIDS) is influenced by unfair computational distribution among many-core NIDS nodes. To avoid such unfair computational distribution, STEAL is designed to dynamically distribute a large volume of traffic among many-core NIDS nodes based on packet service time, which is represented by the deep packet time in many-core NIDS nodes. From experiments, we show that compared to the commonly used load-balancing algorithm based on arrival rate, STEAL increases the number of received packets (i.e., decreases the number of dropped packets) in many-core NIDS. Specifically, by integrating an open source NIDS (i.e. Bro) with STEAL, we show that even under attack-dominant traffic and with many signatures, STEAL can rapidly improve the performance of many-core NIDS to realize high-speed intrusion detection.

• Journal of the Korea Society for Simulation
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• v.15 no.2
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• pp.41-50
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• 2006

The high-speed portable internet service will be served in Korea sooner or later. However, the scheduling method for the packets of various service classes has not been determined clearly yet. An effective packet scheduling for various service classes requiring different QoS is necessary to increase the efficiency of radio channels that are the limiting resource. This paper proposes an improved uplink scheduling method to accommodate more calls and enhance channel efficiency. Suggested scheduling method reflects different channel conditions considering terminal's location within a cell to increase the transmission rate and utility of the channels. According to our simulation results, our proposed scheduling method shows a good performance in the aspect of throughput and capacity of uplink channels.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.641-646
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• 2003

Packet processing speed of routers as well as transmission speed of physical links gives a great effect on IP packet transfer rate in Internet. The router forwards a packet after determining the next hop to the packet's destination. IP address lookup is a main design issue for high performance routers. In this paper, we propose a partitioned compressed-trie for speeding-up IP address lookup algorithms based on tie data structure by exploiting path compression. In the ,proposed scheme, IP prefixes are divided into several compressed-tries and lookup is performed on only one partitioned compressed-trie. Memory access time for IP address lookup is lessen due to compression technique and memory required for maintaining partition does not increased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.613-619
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• 2012

The Long Term Evolution (LTE) system is already able to provide a background of variety services for mobile users with multimedia services such as audio, video, and data. In fact, the High Speed Packet Access plus (HSPA+) solution can greatly enhance bit rates on down-link. However, the supporting for multimedia applications with different QoS (Quality of Service) requirements is not devised yet. Hence, in this paper we propose an effective packet scheduling algorithm based on Proportional Fairness (PF) scheduling algorithms for the LTE. In this proposed packet scheduling scheme, we optimized instantaneous user data rates and the traffic class weight which prioritize user's packets. Finally, we evaluated and showed the performance of the proposed scheduling algorithm through simulations of multimedia traffics being transmitted to users over LTE links in a multi-cell environment.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.440-443
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• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.21-31
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• 2015

The Internet users want to get real-time services for various multi-media applications. Network traffic rate has been rapidly increased, and data amounts that the Internet has to carry have been exponentially increased. A packet is the basic unit in transferring data at the Internet, and packet classification is one of the most challenging functionalities that routers should perform at wire-speed. Among various known packet classification algorithms, area-based quad-trie (AQT) algorithm is one of the efficient algorithms which can lookup five header fields simultaneously. As a representative space decomposition algorithm, the AQT requires a small amount of memory in storing classification rules, but it does not provide high-speed classification performance. In this paper, we propose a new packet classification algorithm by applying a binary search for the codewords of the AQT to overcome the issue of the AQT. Throughout simulation, it is shown that the proposed algorithm provides a better performance than the AQT in the number of rule comparisons with each input packet.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5A
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• pp.517-525
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• 2006

In this paper, we present a high-speed RFID data filtering engine designed to carry out filtering under the conditions of massive data and massive filters. We discovered that the high-speed RFID data filtering technique is very similar to the high-speed packet classification technique which is used in high-speed routers and firewall systems. Actually, our filtering engine is designed based on existing packet classification algorithms, Bit Parallelism and Aggregated Bit Vector(ABV). In addition, we also discovered that there are strong temporal relations and redundancy in the RFID data filtering operations. We incorporated two kinds of caches, tag and filter caches, to make use of this characteristic to improve the efficiency of the filtering engine. The performance of the proposed engine has been examined by implementing a prototype system and testing it. Compared to the basic sequential filter comparison approach, our engine shows much better performance, and it gets better as the number of filters increases.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.50-58
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• 1996

This paper proposes the channel-access protocol suitable to a very high speed photonic WDM network with star configuration, which can provide a high channel utilization and insensitivity to the propagation delay. The proposed protocol employs a control channel and a simple status table to deal with the propagation delay which has been a major limiting factor in the performance of the very high speed optical communication networks. The control channel transmits control information in order to reserve access on data channels, and each node constitutes a status table after the reception of control pckets which holds information about the availbility of destination node and data channel. The proposed protocol is insensitive to the propagation delay time by removing necessity of the retransmission and by allowing parallel transmission of control packet and data packets. It is proved in analysis and discrete event simulation that the proposed protocol is superior in throughput and mean delay, especially at the high load conditions compared to the existing high speed channel-access protocols.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.