• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.340-343
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• 2008

The Soya Warm Current (SWC) is a coastal boundary current, which flows along the coast of Hokkaido in the Sea of Okhotsk. Seasonal and subinertial variations in the SWC are investigated using data obtained by high-frequency (HF) ocean radars, coastal tide gauges, and a bottom-mounted acoustic Doppler current profiler (ADCP). The HF radars clearly capture the seasonal variations in the surface current fields of the SWC. The velocity of the SWC reaches its maximum, approximately 1 m/s, in the summer, and becomes weaker in the winter. The velocity core is located 20 to 30 km from the coast, and its width is approximately 50 km. The almost same seasonal cycle was repeated in the period from August 2003 to March 2007. In addition to the annual variation, the SWC exhibits subinertial variations with a period from 10-15 days. The surface transport by the SWC shows a significant correlation with the sea level difference between the Sea of Japan and Sea of Okhotsk for both of the seasonal and subinertial variations, indicating that the SWC is driven by the sea level difference between the two seas. Generation mechanism of the subinertial variation is discussed using wind data from the European Centre for Medium-range Weather Forecasts (ECMWF) analyses. The subinertial variations in the SWC are significantly correlated with the meridional wind component over the region. The subinertial variations in the sea level difference and surface current delay from the meridional wind variations for one or two days. Continental shelf waves triggered by the meridional wind on the east coast of Sakhalin and west coast of Hokkaido are considered to be a possible generation mechanism for the subinertial variations in the SWC.

• Journal of Microbiology and Biotechnology
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• v.17 no.4
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• pp.701-704
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• 2007

This report describes the full-length sequences of 2HBV clones from a hepatocellular carcinoma (HCC) patient, one with preC mutation (1896A) and the other without preC mutation. The high level of discrepancy in mutation frequency between these 2 strains was observed in the Core (C) region among 4 ORFs. These data support previous results that Korean HBV strains, belonging to genotype C2, are prone to mutations. It is possible that the mutations (BCP and preC mutations) associated with the HBeAg defective production might contribute to the diversity of mutations related to HBV persistence, playing an important role in hepatocarcinogenesis in this patient.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.3
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• pp.288-300
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• 2002

In this paper, a novel method of equalization of RF transceivers is suggested for MIMO(Multiple Input Multiple Output) antenna actively studied for high speed data transmission in the recent IMT-2000 system. The core of suggestion is in equalizing the transfer characteristics of multiple transceivers using feedback and memory during the predefined calibration time. This makes it possible to weight the signals in the intermediate frequency, which is easier in the application of recently developed DoA(Direction of Arrival) algorithms. In addition, the time varying optimum cell formation according to traffic is feasible by antenna beam-forming based on the DoA information. The suggested method of equalizing multiple transceivers are successfully verified using envelope simulation. two outputs. This paper is concerned with the diagnosis of multiple crosstalk-faults in OSM. As the network size becomes larger in these days, the convent.
nal diagnosis methods based on tests and simulation be.
me inefficient, or even more impractical. We propose a simple and easily implementable alg？ithm for detection and isolation of the multiple crosstalk-faults in OSM. Specifically, we develop an algorithm for isolation of the source fault in switc.
ng elements whenever the multiple crosstalk-faults are.
etected in OSM. The proposed algorithm is illustrated by an example of 16$\times$16 OSM.

• Journal of the Korean Ceramic Society
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• v.39 no.12
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• pp.1158-1163
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• 2002

An Ge/B-doped optical fiber with high photosensitivity was fabricated to induce large second-order optical nonlinearity by UV poling. It was found that long period fiber gratings were inscribed on the fiber by the 248 nm KrF excimer laser irradiation with pulse energy of 116 mJ/$cm^2$ and pulse frequency of 10 Hz without hydrogen loading treatment. The photosensitivity was measured by use of the long period fiber grating pair method and the refractive index change of 3.3$10{\times}^{-3}$ was found to be induced in the core of the optical fiber by the KrF excimer laser irradiation of 8.67 kJ/$cm^2$. An H-shaped optical fiber was also fabricated for the UV poling through optimization of the fiber drawing condition.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1455-1461
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• 2012

MIMO-OFDM which is one of core techniques for the high-speed mobile communication system requires the efficient channel estimation method with low estimation error and computational complexity, for accurately receiving data. In this paper, we propose a channel estimation algorithm with low channel estimation error comparing with LS which is primarily employed to the MIMO-OFDM system, and with low computational complexity comparing with MMSE. The proposed algorithm estimates channel vectors based on the LMS adaptive algorithm in the time domain, and the estimated channel vector is sent to the detector after FFT. We also suggest a preamble architecture for the proposed MIMO-OFDM channel estimation algorithm. The computer simulation example is provided to illustrate the performance of the proposed algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.1
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• pp.74-81
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• 2003

In this study, we'd implemented a real time embedded speech recognition system that requires minimum memory size for speech recognition engine and DB. The word to be recognized consist of 40 commands used in a PCS phone and 10 digits. The speech data spoken by 15 male and 15 female speakers was recorded and analyzed by short time analysis method, which window size is 256. The LPC parameters of each frame were computed through Levinson-Burbin algorithm and they were transformed to Cepstrum parameters. Before the analysis, speech data should be processed by pre-emphasis that will remove the DC component in speech and emphasize high frequency band. Baum-Welch reestimation algorithm was used for the training of HMM. In test phone, we could get a recognition rate using likelihood method. We implemented an embedded system by porting the speech recognition engine on ARM core evaluation board. The overall recognition rate of this system was 95%, while the rate on 40 commands was 96% and that 10 digits was 94%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.6
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• pp.1-7
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• 2008

FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. FlexRay communication controller (CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung $0.35\;{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Journal of Sensor Science and Technology
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• v.24 no.6
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• pp.379-384
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• 2015

An infrared image sensor is a core device in a thermal imaging system. The fabrication method of a focal plane array (FPA) is a key technology for a high resolution infrared image sensor. Each pixels in the FPA have $Si_3N_4/SiO_2$ membranes including legs to deposit bolometric materials and electrodes on Si readout circuits (ROIC). Instead of polyimide used to form a sacrificial layer, the feasibility of an amorphous silicon (${\alpha}-Si$) was verified experimentally in a $8{\times}8$ micro-bolometer array with a $50{\mu}m$ pitch. The elimination of the polyimide sacrificial layer hardened by a following plasma assisted deposition process is sometimes far from perfect, and thus requires longer plasma ashing times leading to the deformation of the membrane and leg. Since the amorphous Si could be removed in $XeF_2$ gas at room temperature, however, the fabricated micro-bolomertic structure was not damaged seriously. A radio frequency (RF) sputtered nickel oxide film was grown on a $Si_3N_4/SiO_2$ membrane fabricated using a low stress silicon nitride (LSSiN) technology with a LPCVD system. The deformation of the membrane was effectively reduced by a combining the ${\alpha}-Si$ and LSSiN process for a nickel oxide micro-bolometer.