• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.96-99
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• 2014

In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.105-105
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• 2012

We have developed a photoemission-assisted plasma-enhanced chemical vapor deposition (PAPE-CVD) [1,2], in which photoelectrons emitting from the substrate surface irradiated with UV light ($h{\nu}$=7.2 eV) from a Xe excimer lamp are utilized as a trigger for generating DC discharge plasma as depicted in Fig. 1. As a result, photoemission-assisted plasma can appear just above the substrate surface with a limited interval between the substrate and the electrode (~10 mm), enabling us to suppress effectively the unintended deposition of soot on the chamber walls, to increase the deposition rate, and to decrease drastically the electric power consumption. In case of the deposition of DLC gate insulator films for the top-gate graphene channel FET, plasma discharge power is reduced down to as low as 0.01W, giving rise to decrease significantly the plasma-induced damage on the graphene channel [3]. In addition, DLC thickness can be precisely controlled in an atomic scale and dielectric constant is also changed from low ${\kappa}$ for the passivation layer to high ${\kappa}$ for the gate insulator. On the other hand, negative electron affinity (NEA) of a hydrogen-terminated diamond surface is attractive and of practical importance for PAPECVD, because the diamond surface under PAPE-CVD with H2-diluted (about 1%) CH4 gas is exposed to a lot of hydrogen radicals and therefore can perform as a high-efficiency electron emitter due to NEA. In fact, we observed a large change of discharge current between with and without hydrogen termination. It is noted that photoelectrons are emitted from the SiO2 (350 nm)/Si interface with 7.2-eV UV light, making it possible to grow few-layer graphene on the thick SiO2 surface with no transition layer of amorphous carbon by means of PAPE-CVD without any metal catalyst.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.128.1-128.1
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• 2016

Nitrided-metal gates on the high-${\kappa}$ dielectric material are widely studied because of their use for sub-20nm semiconductor devices and the academic interest for the evanescent states at the Si/insulator interface. Issues in these systems with the Si substrate are the electron mobility degradation and the reliability problems caused from N defects that permeates between the Si and the $SiO_2$ buffer layer interface from the nitrided-gate during the gate deposition process. Previous studies proposed the N defect structures with the gap states at the Si band gap region. However, recent experimental data shows the possibility of the most stable structure without any N defect state between the bulk Si valence band maximum (VBM) and conduction band minimum (CBM). In this talk, we present a new type of the N defect structure and the electronic structure of the proposed structure by using the first-principles calculation. We find that the pair structure of N atoms at the $Si/SiO_2$ interface has the lowest energy among the structures considered. In the electronic structure, the N pair changes the eigenvalue of the silicon-induced gap state (SIGS) that is spatially localized at the interface and energetically located just above the bulk VBM. With increase of the number of N defects, the SIGS gradually disappears in the bulk Si gap region, as a result, the system gap is increased by the N defect. We find that the SIGS shift with the N defect mainly originates from the change of the kinetic energy part of the eigenstate by the reduction of the SIGS modulation for the incorporated N defect.