• The KIPS Transactions:PartC
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• v.9C no.1
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• pp.107-114
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• 2002

In these days, rapid advances of the computer system and the high speed network have made the multimedia services popularized among various applications and services in the internet. Internet live broadcasting, a part of multimedia services, makes it possible to provide not only existing broadcasting services including audio and video but also interactive communications which also expand application scopes by freeing from both temporal and spatial limitation. In the Paper, an interned Personal-live broadcasting server system is developed by allowing individual users to actively create or join live-broadcasting services with such basic multimedia devices as a PC camera and a sound card. As the number of broadcasters and participants increases, concurrent multiple channels are established and groups are to be expanded. The system should also guarantee High Availability (HA) for continuous services even in the presence of partial failure of the cluster. Furthermore, a transmission mode switching is supported to consider network environments in the user system.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.123-132
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• 2005

In this Paper, we present an improvement of switch node for wavelength multiplex optical network. Currently because of quick increase of internet traffic a big network capacity is demanded. Wavelength multiplex optical network Provides the data transfer of high speed and the transparent characteristic of the data. Therefore optic network configuration is the most powerful technology in the future. It will be able to control the massive traffic from the optical network in order to transmit the multimedia information of very many quantify. Consequently the node where the traffic control is Possible, is demanded. The optical switch node which manages efficiently the multiple wavelength was Proposed. This switch is composed of a optical switch module for switching and a wavelength converter module for wavelength conversion. It will be able to compose the switch fabric without optical/electro or electro/optical conversion using optical MEMS(Micro Electro Mechanical Switches) module. Finally, we present the good test result regarding the operational qualify of the switch fabric and the performance of optical signal from the switch node. The proposed switch node of the optic network will be able to control the massive traffic with all optical.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.626-634
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• 2004

In a client-server model, network server systems suffer from both heavy communication and computational loads. While communication channels become increasingly speedy, the existing protocol stack architectures still include mainly three performance bottlenecks of protocol stack processing, system call, and network interrupt overheads. To address these obstacles, in this paper we present a host-independent network system where a network interface card (NIC) is utilized in an efficient manner. First, by offloading network-related portion to the NIC, the host can fully utilize its processing power for other useful purposes. Second, it eliminates the system call overhead, such as context-switching and memory copy operations, since the host communicates with the NIC through its user-level libraries. Third, it a] so reduces the network interrupt operation count as the host handles the interrupt in a segment instead of a packet. The experimental results show that the proposed network system reduces the host CPU overhead for communication system by 68-71%. It also shows that the proposed system improves the communication speed by 11-83% under heavy computational and communication load conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• The Korean Journal of Emergency Medical Services
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• v.14 no.3
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• pp.71-81
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• 2010

Purpose: To minimize an interruption in chest compression, reduce the hands-off time, the American Heart Association has recommended the ratio of chest compression to ventilation ratio to 30:2 from 2005 CPR guideline to 2010 CPR guideline. However, current studies have shown that the hands-off time was > 10 seconds with that method. For this reason, we devised new CPR method that a ventilation to chest compression ratio of 2:30 to reduce pt assessment time and skipped the assessment step of carotid artery pulse would be a more effective way to reduce the hands-off time & the time to set the CPR. According to the more detailed purpose are listed below. 1) We would like to confirm efficiency of a ventilation to chest compression ratio of 2:30 than a chest compression to ventilation ratio of 30:2 to reduce the hands-off time & the time to set the CPR. 2) We would like to evaluate possibility of increasing for chest compression accuracy of a ventilation to chest compression ratio of 2:30 than a chest compression to ventilation ratio of 30:2 3) We would like to evaluate possibility of increasing for ventilation accuracy of a ventilation to chest compression ratio of 2:30 than a chest compression to ventilation ratio of 30:2 Methods: According to 2005 American Heart Association Guidelines, 60 paramedic students(20 students X freshmen, sophomore, junior) performed 5 cycles of 3~ chest compressions : 2 ventilations after A, B, C evaluation with Laerdal Resusci R Anne SkillReporters. After 5 minutes rest, the 60 students performed 5 cycles of 2 ventilations : 30 chest compressions after A, B evaluation with the manikins between 13 and 17 September 2010. The short reports including speed & accuracy of chest compression, respiratory, CPR cycle were gained from the manikins. Hands-off times were measured by assistants. Results: Recently, the importance of high quality CPR was emphasized in order to perform the CPR faster and more accurate. To find out improving the conventional CPR method, we switch the procedure of the compression and the ventilation. By switching the procedure back and forth, we are able to compare the effectiveness of CPR between two type of CPR method which are 2:30 and 30:2 methods. 2:30 is that the breaths is delivered twice, first and perform 30 compressions while 30:2 perform 30 compressions first and give 2 breaths followed by the ABC method. Also, we verify the effectiveness of the hands off time, compression accuracy of the compression through the comparison of the two procedure as mentioned earlier. Consequently research verified that 2:30 is the efficient by providing faster set up delivering more accurate chest compression. Conclusion: 2:30 can minimize a time delay from cardiac standstill until starting the chest compression. In addition, hands-off time which is an interruption in chest compression can be shortened by 2:30 method, which result to effective oxygenation of coronary artery & maintenance of the bloodstream. Once again, performing the 2:30 method provide lessen hands off time and increase the accuracy of the chest compression.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1142-1149
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• 2007

In this paper, the development of wideband MIMO channel sounder and a pilot measurement result is described for research on the multi antenna radio propagation characteristics considering urban environment at microwave frequencies. We developed $4{\times}4$ MIMO(BW:100 MHz) channel sounder using the high speed switching mechanism and periodic pseudo random binary signals method considering next generation mobile communication system. A pilot measurement campaign at the urban area of Bundang is presented for confirmation of system performance. From the analysis of measurement data, wideband path loss exponent of 3.7 and 8 GHz band is 1.79 and 1.76. Average RMS delay spread is 200 ns and 42 ns respectively. From the experiment results, operation of this measurement system is confirmed considering research for a coverage, SNR and channel capacity in urban environment at microwave frequencies.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.1
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• pp.25-39
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• 1986

In this paper, we analyze the performance, particularly the flow control mechanism, of the CCITT X.25 protocol in a packet-switched network. In this analysis, we consider the link and packet layers separately, and investigate the performance in three measures; normalized channel throughput, mean transmission time, and transmission efficiency. Each of these measures is formulated in terms of given protocol parameters such as windos size, $T_1$ and $T_2$ values, message length, and so forth. We model the service procedure of the inpur traffic based on the flow control mechanism of the X.25 protocol, and investigate the mechanism of the sliding window flow control with the piggybacked acknowlodgment scheme using a discrete-time Markov chain model. With this model, we study the effect of variation of the protoccol parameters on the performance of the X.25 protocol. From the numerical results of this analysis one can select the optimal valuse of the protocol parameters for different channel environments. it has been found that to maintain the trasnmission capacity satisfactorily, the window size must be greater than or equal to 7 in a high-speed channel. The time-out value, $T_1$, must carefully be selected in a noisy channel. In a normal condition, it should be in the order of ls. The value of $T_2$ has some effect on the transmission efficiency, but is not critical.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.