• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.2
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• pp.99-108
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• 2020

In the field of aircraft icing prediction, surface roughness has been considered as critical factor because it enhances convective heat transfer and changes local collection efficiency. For this significance, experimental studies have been conducted to acquire the quantitative data of the formation process. Meanwhile, these experiments was conducted under low-speed condition due to the measurement difficulties. However, it has not been investigated that how the flow characteristic of low-speed will effects to the surface roughness. Therefore, the present study conducted experiment under low-speed icing condition, and analyzed the relation between surface roughness characteristics and icing condition. As an analysis method, the dominant parameters used in the previous high-speed experiments are employed, and roughness characteristics are compared. The size of roughness element was consistent with the previous known tendency, but not the smooth zone width.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.36-45
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• 1998

This paper discusses multiple access control aspects for a wireless extension of high-speed asynchronous transfer mode(ATM) networks. One challenging requirement is that mobile systems convey of diverse types of information including voice, computer data, facsimile, and video data that have different quality of service constraints. Basically, a centralized control scheme for a coordinated multiple access is required in order to efficiently accommodate multimedia traffic on wireless links. The proposed scheme dynamically scheduling the mobile terminal, which has data to transfer according to the service, types at base station. In this scheme, the scheduling algorithm is performed on the basis of traffic descriptors and QoS parameters, which required in the connection set up phase. As a consequence, the transmission scheduling is very flexible and can account for the different traffic rate and delay constraints that emerge from voice and data integration. The simulation result shows that the proposed scheme has better performance over other scheduling algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1295-1300
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• 2006

In this paper, we have developed RFID systems with integrated tag location data for efficient logistics information systems. These are consist of RFID readers with GPS module and RFID networks to service tag location data. The developed RFID readers can get location informations Of the tags, transfer them high speed by TCP/IP protocols, and operate as web servers. And we presented a simple service network system based on EPC network to service both location and tag data. The proposed system can be applicable to tracebility or finding locations of the products.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5B
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• pp.465-475
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• 2004

Transport Control Protocol (TCP) has been implemented in software running on CPU in end systems, and the protocol processing has appeared as a new bottleneck due to advanced link technology. TCP processing is a critical issue in Storage Area Network (SAN) such as iSCSL, and the overall performance of the Storage Area Network heavily depends on speed of TCP processing. TCP Engine implemented in hardware reduces the load of CPU in end systems as well as accelerates the protocol processing, and hence high speed data processing is achieved. In this paper, we have proposed a hardware engine for TCP processing. TCP engine consists of three major block, TCP Connection block Rx TCP block and Tx TCP block TCP Connection block is responsible for managing TCP connection states. Rx TCP block is responsible for receive flow which receives packets from network and sends to CPU. Rx TCP performs header and data processing and sends header information to TCP connection block and Tx TCP block It also assembles out-of-ordered data to in-ordered before it transfers data to CPU. Tx TCP block is responsible for transmit flow which transfers data from CPU to network. Tx TCP performs retransmission for reliable data transfer and management of transmit window and sequence number. Various test-cases are used to verify the TCP functions. The TCP Engine is synthesized using 0.18 micron technology and results in 51K gates not including buffers for temporal data storage.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.641-646
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• 2003

Packet processing speed of routers as well as transmission speed of physical links gives a great effect on IP packet transfer rate in Internet. The router forwards a packet after determining the next hop to the packet's destination. IP address lookup is a main design issue for high performance routers. In this paper, we propose a partitioned compressed-trie for speeding-up IP address lookup algorithms based on tie data structure by exploiting path compression. In the ,proposed scheme, IP prefixes are divided into several compressed-tries and lookup is performed on only one partitioned compressed-trie. Memory access time for IP address lookup is lessen due to compression technique and memory required for maintaining partition does not increased.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.9-14
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• 1999

In this paper, a method of one line transmission of 622Mbps to interface a low speed part with a high speed part is introduced instead of H-BUS method of the 10 line transmission of 77.76Mbps in the 10Gbps optical transmission system. For this method, a reframing method to align the received data of 622Mbps transmission to STM(Synchronous Transfer Mode)-64 frame of SDH(Synchronous Digital Hierarchy) is described. Reframing is designed with VHDL and applied in the 10G-S4 ASIC of T14U board of 10Gbps optical transmission system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.663-668
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• 2003

With the advent of high speed networking technology, computers connected to the high-speed networks tend to consume more of their CPU cycles to process data. So one of the solutions to improve the performance of the computers is to reduce the CPU cycles for processing the data. As the consumption of the CPU cycles is increased in proportion to the number of the packets per second to be processed, reducing the number of the packets per second by increasing the length of the packet is one of the solutions. In order to meet this requirement, two types of jumbo packets such as jumbograms and jumbo frames have already been standardized or being discussed. In case that the jumbograms and general packets are interleaved and scheduled together in a router, the jumbogrms may deteriorate the QoS of the general packets due to the transfer delay. They also frequently exhaust the memory with storing the huge length of the packets. This produces the congestion state easily in the router that results in the loss of the packets. In this paper, we analyze the problems in processing the jumbo packets and suggest a noble solution to overcome the problems.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.311-315
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• 2008

The switching fabric used to make high speed switching for packet transfer between input and output interface in recent internet environments. Without making any changes in order to remain ATM switching fabric, the existing structures should split/reassemble a packet to certain size, set aside cross-point buffer and will put loads on the system. In this paper, we proposed a new switch architecture, which has separated data memory plane and switching plane packet data will be stored on the separate memory structure and simultaneously only the part of the memory address pointers can pass the switching fabric. The small mini packets which have address pointer and basic information would be passed through the switching fabric. It is possible to achieve the remarkable switching performance than other switch fabrics with contending variable length packets.