• 한국전기전자재료학회논문지
• /
• 제14권9호
• /
• pp.703-703
• /
• 2001

• 한국전기전자재료학회논문지
• /
• 제14권9호
• /
• pp.707-713
• /
• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was requirdfo the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gest thinner, micro-scratches are becoming as major defects. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}{\textrm}{m}$ point of use (POU) filter, which is depth-type filter and has 80% filtering efficiency for the 1.0${\mu}{\textrm}{m}$ size particle. In this paper, we studied the relationship between defect generation and polished wafer counts to understand the exact efficiency fo the slurry filteration, and to find out the appropriate pad usage. Our experimental results showed that it sis impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate, and to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of depth type filter.