• 한국주조공학회지
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• 제22권6호
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• pp.309-314
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• 2002

The effect of mold density and evacuation on surface defect of high chromium cast iron upon EPC process was investigated. Under evacuation of $0.1{\sim}0.3$ atm, surface defects were carbon defect, burn on and misrun. Carbon defect was augmented by increasing mold density from 0.011 g/$cm^3$ to 0.03 g/$cm^3$ under evacuation of $0.1{\sim}0.3$ atm, but carbon defect was decreased by increasing evacuation from 0.1 to 0.3 atm. Burn-on wasn't found under evacuation of 0.1 atm regardless of mold density, but burn-on was augmented by increasing evacuation from 0.2 to 0.3 atm and decreased by reducing mold density. Misrun was only found under 0.1 atm evacuation and 0.011 g/$cm^3$ mold density.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2000년도 특별강연 및 추계학술발표대회 개요집
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• pp.201-203
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• 2000

In this study, effect of welding parameters on the defect density in the weldments produced by high frequency electric resistance welding process. The defect density measured by X-ray radiography showed a W-type curve as a function of heat input rate. The mechanisms of the such behavior were discussed based on the chemical compositions of the oxides formed at the weldments.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Transactions on Electrical and Electronic Materials
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• 제18권2호
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• pp.70-73
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• 2017

We investigated n-i-p type single junction hydrogenated amorphous silicon oxide solar cells. These cells were without front surface texture or back reflector. Maximum power point efficiency of these cells showed that an optimized device structure is needed to get the best device output. This depends on the thickness and defect density ($N_d$) of the active layer. A typical 10% photovoltaic device conversion efficiency was obtained with a $N_d=8.86{\times}10^{15}cm^{-3}$ defect density and 630 nm active layer thickness. Our investigation suggests a correlation between defect density and active layer thickness to device efficiency. We found that amorphous silicon solar cell efficiency can be improved to well above 10%.

• 한국세라믹학회지
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• 제54권2호
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• pp.75-85
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• 2017

Thermoelectric is a key technology for energy harvesting and solid-state cooling by direct thermal-to-electric energy conversion (or vice versa); however, the relatively low efficiency has limited thermoelectric systems to niche applications such as space power generation and small-scale or high-density cooling. To expand into larger scale power generation and cooling applications such as ATEG (automotive thermoelectric generators) and HVAC (heating, ventilation, and air conditioning), high-performance bulk thermoelectric materials and their low-cost processing are essential prerequisites. Recently, the performance of commercial thermoelectric materials including $Bi_2Te_3$-, PbTe-, skutterudite-, and half-Heusler-based compounds has been significantly improved through non-equilibrium processing technologies for defect engineering. This review summarizes material design approaches for the formation of multi-dimensional and multi-scale defect structures that can be used to manipulate both the electronic and thermal transport properties, and our recent progress in the synthesis of conventional thermoelectric materials with defect structures is described.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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• pp.105-106
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• 1998

Evaluation of def3ects by etch-ppit formation was studied. A NaOH(30 mol%) etchant was found useful for etch-ppit developpment on ZnSe-based eppilayers grown on (001) gaAs. And a H3ppO4(85 mol%) was used in order to developp etch-ppits on GaN-base eppilayers grown on (0001) Al2O3 After etch-ppit formation on the surfsce. Transmission Electron Microscoppy(TEM) was cppmdicted. By etch-ppit developpment and TEM observation we could determine the defect typpes by etch-ppit configurfations and found origin of etch-ppit in the cse of ZnSe-based materials. Based uppon these results we can do defect identification by etch-ppit test simpply. In the case of GaN-based materials we could evaluate nanoppippe density. however high density of threading dislocations in GaN eppilayers were not revealed by etch-ppit developpment. Based uppon these results we can evaluate the nanoppippe density which difficult to evaluate using TEM beacause of its small size(diameter). And at ppresent status direct matching of etch-ppit density to dislocation density would make severe mistake.

• 한국재료학회지
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• 제11권9호
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• pp.781-785
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• 2001

The thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystal was investigated by applying high temperature annealing ($\geq$$1100^{\circ}C$) and non-agitated Secco etching. For evaluation of the effect of LP upon device performance/yield, commercial DRAM and ASIC devices were fabricated. The results indicated that high temperature annealing generates LPs whereas it decreases FPD density drastically. However, the origins of FPD and LP seemed to be quite different by not showing any correspondence to their density and the location of LP generation and FPD extinction. By not showing any difference between the performance/yield of devices whose design rule is larger than 0.35 $\mu\textrm{m}$, LP seemed not to have detrimental effects on the performance/yield.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.15-15
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• 2018

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2572-2574
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• 1999

본논문은 제작된 다이오드 switching시 나타난 전류 증가현상을 관측하고 그 원인을 분석했다. 증가현상을 보이는 구조는 다이오드에 전자를 조사한 소자로 proton을 조사한 구조에 비해서 접합부근에 high defect density 영역이 형성된다. Reverse recovery시에 이영역에 높은 역방향 전계가 형성, 조사에 순간적으로 전류가 증가하게 한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.17-20
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• 1998

Thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystals was investigated by applying high temperature ($\geq$1100$^{\circ}C$) annealing and non-agitation Secco etching. For evaluation of the effect of LP upon device performance / yield, DRAM and ASIC devices were fabricated. The results indicate that high temperature annealing generates LPs whereas it decreases FPD density drastically, and LP does not have detrimental effects on the performance /