• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.518-525
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• 2016

This paper presents the characteristics of non-fundamental multi-mode combustion instability and the effects of high-harmonic components on the Rayleigh criterion. Phenomenological observations of multi-harmonic-mode dynamic pressure waves regarding the intensity of harmonic components and the source of wave distortion have been explained by introducing examples of second- and third-order harmonics at various amplitudes. The amplitude and order of the harmonic components distorted the wave shapes, including the peak and the amplitude, of the dynamic pressure and heat release, and consequently the temporal Rayleigh index and its integrals. A cause-and-effect analysis was used to identify the root causes of the phase delay and the amplification of the Rayleigh index. From this analysis, the skewness of the dynamic pressure turned out to be a major source in determining whether multi-mode instability is driving or damping, as well as in optimizing the combustor design, such as the mixing length and the combustor length, to avoid unstable regions. The results can be used to minimize errors in predicting combustion instability in cases of high multi-mode combustion instability. In the future, the amount of research and the number of applications will increase because new fuels, such as fast-burning syngases, are prone to generating multi-mode instabilities.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.132-140
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• 2001

A universal motor is a small dc series machine motor that is designed to operate from an ac machine. The characteristics of universal motors are high no-load and staring torque. Because of the high operating speed, the size of these motors for a given hp rating is typically smaller that other fractional hp ac machine, making it ideal for hand-held tools and appliances where weight, compactness, and speed are importance factors. A phase-angle control with AC drive system gains a high popularity due to their simple implementation, but contains the disadvantage of their poor input power factor, subharmonic current. Pulse width modulation control with DC drive systems increase the power factor as without delay phase angle. This paper analyzed the subharmonic characteristics of the phase angle control system that is controlled by zero voltage crossing similar to traditional method, and the dc chopper system that is used PWM.

• Journal of Power Electronics
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• v.17 no.2
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• pp.389-397
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• 2017

A control scheme for stand-alone inverters that utilizes an inductor current observer (ICO) is proposed. The proposed method measures disturbance load currents using a current sensor and it estimates the inductor current using the ICO. The filter parameter mismatch effect is analyzed to confirm the ICO's controllability. The ICO and controllers are designed in a continuous-time domain and transferred to a discrete-time domain with a digital delay. Experimental results demonstrate the effectiveness of the ICO using a 5-kVA single-phase stand-alone inverter prototype. The experimental results demonstrate that the observed current matches the actual current and that the proposed method can archive a less than 2.4% total harmonic distortion (THD) sinusoidal output waveform under nonlinear load conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.10
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• pp.1487-1493
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• 2013

A new simple control method for active power filter, which can realize the complete compensation of harmonics is proposed. In the proposed scheme, a model-based digital current control strategy is presented. The proposed control system is designed and implemented in a form referred to as internal model control structure. This method provides a convenient way for parameterizing the controller in term of the nominal system model, including time-delays. As a result, the resulting controller parameters are directly set based on the power circuit parameters, which make tuning of the controllers straightforward task. In the proposed control algorithm, overshoots and oscillations due to the computation time delay is prevented by explicit incorporating of the delay in the controller transfer function. In addition, a new compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Resonance model has an infinite gain at resonant frequency, and it exhibits a band-pass filter. Consequently, the difference between the instantaneous load current and the output of this model is the current reference signal for the harmonic compensation.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.56 no.3
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• pp.136-141
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• 2007

In this paper, a new simple control method for active power filter which can realized the complete compensation of the harmonic currents is proposed. In the proposed scheme, a compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Deadbeat control is employed to control the active power filter. The switching pulse width based SVM(Space Vector Modulation) is adopted so that the current of active power filter is been exactly equal to its reference at the next sampling instant. To compensate the computation delay of digital controller, the prediction of current is achieved by the current observer with deadbeat response.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.618-628
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• 2016

Active power filter (APF) has been proved as a flexible solution for compensating the harmonic distortion caused by nonlinear loads in power distribution power systems. Digital repetitive control can achieve zero steady-state error tracking of any periodic signal while the sampling points within one repetitive cycle must be a known integer. However, the compensation performance of the APF would be degradation when the grid frequency varies. In this paper, an improved repetitive control scheme with frequency adaptive capability is presented to track any periodic signal with variable grid frequency, where the variable delay items caused by time-varying grid frequency are approximated with Pade approximants. Additionally, the stability criterion of proposed repetitive control scheme is given. A three-phase shunt APF experimental platform with proposed repetitive control scheme is built in our laboratory. Simulation and experimental results demonstrate the effectiveness of the proposed repetitive control scheme.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.325-330
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• 2012

A single-phase PVPCS(photovoltaic power conditioning system) that contains a single phase dc-ac inverter tends to draw an ac ripple current at twice the out frequency. Such a ripple current may shorten passive elements life span and worsen output current THD. As a result, it may reduce the efficiency of the whole PVPCS system. In this paper, the ripple current propagation is analyzed, and two methods to reduce the ripple current are proposed. Firslyt, this paper presents notch filter with IP voltage controller to reject specific current ripple in single-phase PVPCS. The notch filter can be designed that suppress just only specific frequency component and no phase delay. The proposed notch filter can suppress output command signal in the ripple bandwidth for reducing output current THD. Secondly, for reducing specific current ripple, the other method is feed-forward compensation to incorporate a current control loop in the dc-dc converter. The proposed notch filter and feed-forward compensation method have been verified with computer simulation and simulation results obtained demonstrate the validity of the proposed control scheme.