• Journal of Astronomy and Space Sciences
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• v.25 no.4
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• pp.347-360
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• 2008

In this paper, a Hardware-In-the-Loop simulator to simulate attitude control of space craft using momentum wheels is developed. The simulator consists of a spherical air bearing system allowing rotation and tilt in all three axes, three momentum wheels for actuation, and an AHRS (Attitude Heading Reference System). The simulator processes various types of data in PC104 and wirelessly communicates with a host PC using TCP/IP protocol. A simple low-cost momentum wheel assembly set and its drive electronics are also developed. Several experiments are performed to test the performance of the momentum wheels. For the control performance test of the simulator, a PID controller is implemented. The results of experimental demonstrations confirm the feasibility and validity of the Hardware-In-the-Loop simulator developed in the current study.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.1-10
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• 1998

In this paper, a new hardware-software patitioning algorithm is presented, in which the system behavioral description containing a mixture of hardware and softwae components is partitioned into the hardware part and the software part. In this research, new techniques to optimally partition a mixed system under certain specified constaints such as performance, area, and delay, have been developed. During the partitioning process, the overhead due to the communication between the hardware and software parts are considered. New featues have been added to adjust the hierarchical level of partitioning. Power consumption, memory cost, and the effect of pipelining can also be considered during partitioning. Another new feature is the ability to partition a DSP system under throughput constraints. This feature is important for real time processing. The developed partitioning system can also be used to evaluate various design alternatives and architectures.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1624-1634
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• 1995

Conventional full search block matching algorithm for motion estimation is computationally intensive and the resulting hardware cost is very high. In this paper, we present an efficient block matching algorithm using a 16:1 subsampling technique, and describe its hardware design. The algorithm reduces the number of pixels in calculating the mean absolute difference at each search location, instead of reducing the search locations.The algorithm is an extension of the block mating algorithm with 4:1 subsampling proposed by Liu and Zaccarin such that the amount of computation is reduced by a fact of 4(16 compared to the full search block matching algorithm) while producing similar performance.The algorithm can efficiently be designed into a hardware for real-time applications.

• Communications for Statistical Applications and Methods
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• v.12 no.3
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• pp.697-704
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• 2005

Computer software has gradually become an indispensable elements in many aspects of our daily lives and an important factor in numerous systems. In recent years, it is not unusual that the software cost is more than the hardware cost in many situations. In addition to the costs of developing software, the repair cost resulting from the software failures are even more significant. In this paper, a cost model with warranty cost, time to remove each fault detected in the software system, and delivery delay cost is developed. We use a software reliability model based on non-homogeneous Poisson process (NHPP). We discuss the optimal release policies to minimize the expected total software cost. Numerical examples are provided to illustrate the results.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• Journal of Multimedia Information System
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• v.3 no.3
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• pp.63-68
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• 2016

Environmental downtime produces a significant cost to organizations and makes them unable to do business because what happens in the data center affects everyone. In addition, the amount of electrical energy consumed by data centers increases with the amount of computing power installed. Installation of physical Information Technology and facilities related to environmental concerns, such as monitoring temperature, humidity, power, flood, smoke, air flow, and room entry, is the most proactive way to reduce the unnecessary costs of expensive hardware replacement or unplanned downtime and decrease energy consumed by servers. In this paper, we present remote system for monitoring datacenter implementing using open-source hardware platforms; Arduino, Raspberry Pi, and the Gobetwino. The sensed data displayed through Arduino are transferred using Gobetwino to the nearest host server such as temperature, humidity and distance every time an object hitting another object or a person coming in entrance. The raspberry Pi records the sensed data at the remote location. The objective of collecting temperature and humidity data allows monitoring of the server's health and getting alerts if things start to go wrong. When the temperature hits $50^{\circ}C$, the supervisor at remote headquarters would get a SMS, and then they would take appropriate actions to reduce electrical costs and preserve functionality of servers in data centers.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.2
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• pp.181-188
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• 2011

A simulation technique, which simulate dynamic motion and communication environments of ship in the lab, is needed in order to reduce the testing cost when we evaluate the transfer alignment performance of shipboard INS. Hardware-In-the-Loop Simulation(HILS) can be used as an effective test method for those system because it can provide flexible and realistic simulation environments, various test scenario, and repeated test environment in the lab without additional cost and person. This paper presents the methods for implementing the real time HILS environment for testing transfer alignment performance of shipboard INS. It includes real time executive for controlling realtime simulation and calculating the ship motion, communication method for interfacing between the systems, and coordinate transformation method for converting real ship coordinate attitude data to lab coordinate attitude data.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.3689-3700
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• 2016

It is not practically feasible to apply hardware-based fault-tolerant schemes, such as hardware replication, in mobile devices. Therefore, software-based fault-tolerance techniques, such as checkpoint and rollback schemes, are required. In checkpoint and rollback schemes, the optimal checkpoint interval should be applied to obtain the best performance. Most previous studies focused on minimizing the expected execution time or response time for completing a given task. Currently, most mobile applications run in real-time environments. Therefore, it is extremely essential for mobile devices to employ optimal checkpoint intervals as determined by the real-time constraints of tasks. In this study, we tackle the problem of determining the optimal inter-checkpoint interval of checkpoint and rollback schemes to maximize the deadline meet ratio in real-time systems and to build a probabilistic cost model. From this cost model, we can numerically find the optimal checkpoint interval using mathematical tools. The performance of the proposed solution is evaluated using analytical estimates.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.500-504
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• 2007

In this paper, the induction motor rotor fault diagnosis system using current signals, which are measured using axis-transformation method, and speed, which is estimated using current information, are presented. In inverter-fed motor drives unlike line-driven motor drives the stator currents have numerous harmonics components and therefore fault diagnosis using stator currents is very difficult. The current and speed signal for rotor fault diagnosis needs to be precise. Also, high resolution information, which means the diagnosis system, demands additional hardware such as low pass filter, high resolution ADC, encoder and etc. Therefore, the proposed axis-transformation and speed estimation method are expected to contribute to low cost fault diagnosis systems in inverter-fed motor drives without the need for an encoder and any additional hardware. In order to confirm validity of the developed algorithms, various experiments for rotor faults are tested and the line current spectrum of each faulty situation using Park transformation and speed estimation method are compared with the results obtained from fast Fourier transforms.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.717-720
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• 1998

In this paper, we propose a VLSI architecture for implementing a crecently proposed fast block matching algorithm, which is called the HSBMA3S. The proposed architecture consists of a systolic array based basic unit and two shift register arrays. And it covers a search range of -32 ~+31. By using a basic unit repeatedly, we can redcue the number of gates. To implement the basic unit, we can select one among various conventional systolic arrays by trading-off between speed and hardware cost. In this paper, the architecture for the basic unit is selected so that the hardware cost can be minimized. The proposed architecture is fast enough for low bit-rate applications (frame size of 352x288, 30 frames/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic unit, the architecture can be used for the higher bit-rate application of the frame size of 720*480 and 30 frames/sec.