• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.967-971
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• 2009

The histogram equalization algorithm is the most crucial algorithm for image enhancement. Since its direct hardware implementation always requires a divider or multiplier, its implementation cost tends to increas as the image resolution is increased or diverse image resolutions are handled. In this paper, we propose a divider-free reconstruction of histogram equalization algorithm and the corresponding hardware architecture. The logic synthesis results show that the proposed scheme can reduce the logic gate count by 84.2% compared to the conventional implementation example when the UXGA resolution is considered.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.37-44
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• 2010

New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.

• Journal of Software Assessment and Valuation
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• v.15 no.2
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• pp.95-100
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• 2019

In this paper, we propose a simple hardware reporting method for errors in soft-RAID systems of Linux OS. Compared with other reporting methods, the proposed method displays error status intuitively without any additional access process such as log-in process or home-page access. In particular, the server actively displays the error status, so the administrator can take immediate action. In order to confirm the effectiveness of the proposed method, the experimental circuit was constructed and the experimental results showed that the error was actively displayed when an error occurred in the storage device. As such, a soft-RAID system can perform almost the same function as a hardware RAID system, thereby ensuring server data reliability at low cost.

• Journal of Communications and Networks
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• v.7 no.4
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• pp.401-407
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• 2005

Simulations are currently an essential tool to develop and test wireless sensor networks (WSNs) protocols and to analyze future WSNs applications performance. Researchers often simulate their proposals rather than deploying high-cost test-beds or develop complex mathematical analysis. However, simulation results rely on physical layer assumptions, which are not usually accurate enough to capture the real behavior of a WSN. Such an issue can lead to mistaken or questionable results. Besides, most of the envisioned applications for WSNs consider the nodes to be at the ground level. However, there is a lack of radio propagation characterization and validation by measurements with nodes at ground level for actual sensor hardware. In this paper, we propose to use a low-computational cost, two slope, log-normal path­loss near ground outdoor channel model at 868 MHz in WSN simulations. The model is validated by extensive real hardware measurements obtained in different scenarios. In addition, accurate model parameters are provided. This model is compared with the well-known one slope path-loss model. We demonstrate that the two slope log-normal model provides more accurate WSN simulations at almost the same computational cost as the single slope one. It is also shown that the radio propagation characterization heavily depends on the adjusted model parameters for a target deployment scenario: The model parameters have a considerable impact on the average number of neighbors and on the network connectivity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.111-120
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• 2005

A cost effective three-dimensional color gamut mapping architecture is described. The conventional three-dimensional reduced resolution look-up table is considered and the concept of three-dimensional reduced resolution difference look-up table is introduced for cost effective and real-time color gamut mapping. The overall architecture uses one-dimensional memory decomposition of three-dimensional gamut mapping look-up table, three-dimensional interpolation and simple addition operation for generating the final gamut mapped colors. The required computational cost is greatly reduced by look-up table resolution adjustment and further reduced by the gamut mapping rule modification. The proposed architecture greatly reduces the required memory size and hardware complexity compared to the conventional method and it is suitable for real-time applications. The proposed hardware is suitable for FPGA and ASIC implementation and could be applied to the real-time display quality enhancement purposes.

• Journal of Power Electronics
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• v.12 no.1
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• pp.75-82
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• 2012

Elimination of rotor position sensors mechanically coupled with the rotor shaft is attractive to variable speed drives primarily due to increased system reliability and cost reduction. In this regard, search for a simple and robust position sensorless control has been intensified in past few years specifically for low-cost, high-volume applications such as home appliances. This paper describes a new parameter insensitive position sensorless control for switched reluctance motor (SRM) drives satisfying such a need in this market segment. Two consecutive switch-on times of the controllable switch in hysteresis current control are compared to estimate the rotor position and speed. The proposed sensorless control algorithm is very simple to implement since it does not depend on extensive computation or any additional hardware. In addition, the proposed method is robust in that its dynamic performance is least affected by system parameter variations. The proposed approach is demonstrated on a single-controllable-switch-converter-driven SRM with two-phases that lends itself to a system with low cost and compact packaging which comes close to the intended applications. Analysis and simulation results followed by experimental verification are presented to demonstrate the feasibility of the proposed sensorless control method.

• Journal of Communications and Networks
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• v.1 no.3
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• pp.201-212
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• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1330-1331
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• 1995

This paper deals with the design of conductor stringing of KEPCO 765kV transmission line. The main subject in the design of conductor stringing is the determination on what the stringing tension is. According to the stringing tension, the weight and height of towers and the strength necessary for conductor, hardware, insulator vary, and the construction cost and the reliability of tower are affected largely. Therefore, in order to determine the optimum condition for stringing conductors, We appraised various items : estimation of economic comparision, strength appraisal of conductor, hardware, insulator, etc. After studying these entirely, we present the condition of condutor stringing for KEPCO 765kV transmission line.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.575-580
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• 2003

In this paper, we develop a control hardware such as an FPGA based general purpose controller with a DSP board to solve nonlinear control problems. PID control algorithms are implemented in an FPGA and neural network control algorithms are implemented in a DSP board. PID controllers implemented on an FPGA was designed by using VHDL to achieve high performance and flexibility. By using high capacity of an FPGA, the additional hardware such as an encoder counter and a PWM generator, can be implemented in a single FPGA device. As a result, the noise and power dissipation problems can be minimized and the cost effectiveness can be achieved. In order to show the performance of the developed controller, it was tested for controlling nonlinear systems such as an inverted pendulum.