• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.221-226
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• 2006

Around 2002, the United States Coast Guard (USCG) identified a need to re-capitalize their Reference Station (RS) and Integrity Monitor (IM) equipment used in the Nationwide Differential Global Position System (NDGPS). Commercially available off-the-shelf differential RS and IM equipment lacked the open architecture required to support long-term goals that include future system improvements such as use of new civil frequencies on L2 and L5 and realization of a higher rate NDGPS beacon data channel intended to support RTK. The first step in preparing for this future NDGPS was to port current RTCM SC-104 compatible RS and IM functionality onto an open architecture PC-based platform. Trimble's product Charisma is a PC-based RS and IM software designed to meet these USCG goals. In fact USCG engineers provided key designs and design insights throughout the development. We cannot overstate the contribution of the USCG engineers. Fundamental requirements for this effort were that it be sufficiently flexible in hardware and software design to support fluid growth and exploitation of new signals and technologies as they become available, yet remain backward compatible with legacy user receivers and existing site hardware and system architecture. These fundamental goals placed an implicit adaptability requirement on the design of the replacement RS and IM. Additionally, project engineers were to remain focused on sustaining the high level of differential GPS service that 1.5 million legacy users have come to depend on. This paper will present new hardware and software (i.e., Trimble's Charisma software) architecture for the next generation NDGPS RS and IM. This innovative approach to engineering on an open architecture PC-based platform allows the system to continue to fulfill legacy NDGPS system requirements and allows the USCG and others to pursue a scalable hardware re-capitalization strategy. We will use the USCG's recapitalization project to explain the essential role of the Charisma software.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.212-226
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• 2014

This paper presents the design and implementation of a pipelined architecture and a method for real-time human detection using depth image from a Time-of-Flight (ToF) camera. In the proposed method, we use Euclidean Distance Transform (EDT) in order to extract human body location, and we then use the 1D, 2D scanning window in order to extract human joint location. The EDT-based human extraction method is robust against noise. In addition, the 1D, 2D scanning window helps extracting human joint locations easily from a distance image. The proposed method is designed using Verilog HDL (Hardware Description Language) as the dedicated hardware architecture based on pipeline architecture. We implement the dedicated hardware architecture on a Xilinx Virtex6 LX750 Field Programmable Gate Arrays (FPGA). The FPGA implementation can run 80 MHz of maximum operating frequency and show over 60fps of processing performance in the QVGA ($320{\times}240$) resolution depth image.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.463-464
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• 2007

This paper presents the hardware-based genetic algorithm, written in VHDL. Due to parallel computation and no function call overhead, a hardware-based GA advantage a speedup over a software-based GA. The proposed architecture is constructed on a field-programmable gate arrays, which are easily reconfigured. Since a general-purpose GA requires that the fitness function be easily changed, the hardware implementation must exploit the reprogrammability.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.176-185
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• 1996

In this paper, we present the modified CMA (constant modulus algorithm) and LMS (least mean square) algorithms for digiCipher system with reduced hardware cost, in which the pipelined architecture is employed. They yield the performance comparable to that using floating-point operations. We show the effecstiveness of the proposed architecture through the implementation results using VHDL.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.87-90
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• 2003

This paper presents a variable block size motion estimation (ME) algorithm and hardware architectures dedicated to H.264/AVC. Proposed ME architecture can achieve real-time processing for 720$\times$480@30Hz with search range of [-64, +63] in the horizontal and [-32, +31] in the vertical direction at integer-pel accuracy and upto 7 reference frames at the operating frequency of 54MHz.

• Interaction and multiscale mechanics
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• v.6 no.2
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• pp.197-210
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• 2013

A fundamental trend of processor architecture evolving towards exaflops is fast increasing floating point performance (so-called "free" flops) accompanied by much slowly increasing memory and network bandwidth. In order to fully enjoy the "free" flops, a numerical algorithm of PDEs should request more flops per byte or increase arithmetic intensity. A meshfree/GFEM approximation can be the class of the algorithm. It is shown in a GFEM without extra dof that the kind of approximation takes advantages of the high performance of manycore GPUs by a high accuracy of approximation; the "expensive" method is found to be reversely hardware-efficient on the emerging architecture of manycore.

• ETRI Journal
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• v.37 no.4
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• pp.772-779
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• 2015

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.9
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• pp.1373-1378
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• 2017

This paper presents a basic ECU(Electronic Control Unit) hardware development procedure for the functional safety of in-vehicle network systems. We consider complete hardware redundancy as a safety mechanism for in-vehicle communication network under the assumption of the wired network failure such as disconnection of a CAN bus. An ESC (Electronic Stability Control) system is selected as an item and the required ASIL(Automotive Safety Integrity Level) for this item is assigned by performing the HARA(Hazard Analysis and Risk Assessment). The basic hardware architecture of the ESC system is designed with a microcontroller, passive components, and communication transceivers. The required ASIL for ESC system is shown to be satisfied with the designed safety mechanism by calculation of hardware architecture metrics such as the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric).

• Journal of IKEEE
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• v.24 no.3
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• pp.895-900
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• 2020

In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resources are reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOA resource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (Multi Operand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter), hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardware architecture design for BSPE Core.

• ETRI Journal
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• v.32 no.2
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• pp.330-332
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• 2010

We propose a new matched filter architecture for chirp spread spectrum in IEEE 802.15.4a. By using relations among the four subchirps, the proposed architecture comprises four subfilters utilizing only a set of coefficients matched to the first subchirp. The four subfilters share adders and registers, and as a result, the required adders and registers for implementation are reduced.