• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.872-875
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• 1995

The strategy of open architecture control system intends to integrate manufacturing components on a single platform, so that a particular component can be easily added and/or replaced. Therefore, the control scheme is neither hardware dependent nor software dependent. In this paper a modular and object oriented approach for the open architecture structure of control systems is invesigated. A standard reference model for genetic manufacturer system, which consists of three modules; hardware module, operating system module, and application software module, is first proposed. Then a standard reference model for open architecture robot control system is suggested.

• Proceedings of the KOSOMBE Conference
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• v.1994 no.12
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• pp.92-95
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• 1994

As computer systems to make medical practice easy are widely used, a special hardware system processing medical data fast becomes more important. To meet the urgent demand for high speed image processing, especially image compression and decompression, we designed and implemented the medical image CODEC (COder/BECoder) based on MISD(Multiple Instruction Single Data stream) architecture to adopt parallelism in it. Considering not being a standart scheme of medical mage compression/decompress ion, the CODEC is designed programable and general. In this paper, we use JPEG (Joint Photographic Experts Group) algorithm to process images fast and evalutate it.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.784-787
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• 1999

This paper describes a direct digital frequency synthesizer using the CORDIC algorithm, which can be implemented efficiently for a digital sinusoid synthesis. To optimize the hardware design parameters, we perform numerical analysis of the quantization effects for the CORDIC-based architecture. A pipelined architecture is employed to obtain a high data throughput,. We estimate and summarize its hardware costs for a variable accuracy, and a CORDIC-based architecture for 9 bit accuracy is emulated in FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.227-233
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• 2006

In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.93-102
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• 2010

The FMCW(Frequency Modulation Continuous Wave) radar possesses range-velocity ambiguity to identify the correct combination of beat frequencies for each target in the multi-target situation. It can lead to ghost targets and missing targets, and it can reduce the detection probability. In this pap er, we propose an effective identification algorithm for the correct pairs of beat frequencies and the signal processing hardware architecture to effectively support the algorithm. First, using the correlation of the detected up- and down-beat frequencies and Doppler frequencies, the possible combinations are determined. Then, final pairing algorithm is completed with the power spectrum density of the correlated up- and down-beat frequencies. The proposed hardware processor has the basic architecture consisting of beat-frequency registers, pairing table memory, and decision unit. This method will be useful to improve the radar detection probability and reduce the false alarm rate.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.2
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• pp.193-199
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• 2017

In this paper, we proposed an architecture of error detection in $Z_N$ operations using $Z_{(2^r-1)N}$. The error detection can be simply constructed in hardware. The hardware overheads are only 50% and 1% with respectively space and time complexity. The architecture is very efficient because it is detection 99% for 1 bit fault. For 2 bit fault, it is detection 99% and 50% with respective r=2 and r=3.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.417-433
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• 1997

A real-time operating system has focused primary on techniques to minimize processing time, with a secondary emphasis on system reliability issues. Conversely, fault-tolerant system has concentrated on using recourse and information redundancy to maximize the availability and reliability of the system, with a lesser emphasis on performance. We have developed a fault-tolerant and real-time operations system which support a powerful concurrent runtime environment under the above requirements. In this paper, we present an overview of real-time systems, design and implementation of a duplex architecture using advanced concepts and technologies such as fast " fault detection", "fault isolation" and "fault recovery" Because the duplex architecture has two dentical hardware elements and has several recovery steps and hierarchy to facilitate a fast recovery which must be proceeded by a prompt fault detection and isolation. Thus it makes possible to minimize the overhead of the systems including hardware and software and guarantee the service continuity of he systems.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.