• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.533-534
• /
• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• 전자공학회논문지 IE
• /
• v.46 no.2
• /
• pp.7-10
• /
• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.17-25
• /
• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.10
• /
• pp.57-64
• /
• 2000

In this paper, we propose the new hardware architecture which implements the stereo matching algorithm using the dynamprogrammethod. The proposed MOEPE(Merged Odd-Even PE) architecture operates in the systolic manner and finds the disparities form the intensities of the pixels on the epipolar line. The number of PEs used in the MOEPE architecture is the same number of the range constraint, which reduced the nuMber of the necessary PEs draMatically compared to the traditional method which uses the PEs with the same number of pixels on the epipolar line. For the normal sized images, the numof the MOEPE architecture is less than that of the PEs in the traditional method by 25${\times}$The proposed architecture is modeled with the VHDL code and simulated by the SYNOPSYS tool.

• Journal of Broadcast Engineering
• /
• v.1 no.2
• /
• pp.152-164
• /
• 1996

This paper describes the hardware architecture and implementation trade-offs of the Grand Alliance HDTV video encoder system. The implemented video encoder accepts video in 1125 line(30Hz) interlaced format, and produces a bit-stream compliant with the motion picture experts group version 2(MPEG-2) standards. The encoder processing includes large- area motion estimation and an advanced rate control mechanism. To keep the system complexity realizable, we adopt a fast hierarchical motion estimation method and developed its hardware architecture. Furthermore an adaptive perceptual quantization method is adopted to improve the perceptual quality. The developed system Is based on the 4-way parallel processing architecture and is implemented by using programmable IC, memory IC, and special-purpose processors such as DCT and motion estimation processors.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.19-25
• /
• 2006

The fast processing ability of an RTOS (Real Time Operating System) is one of important factors in determining the performance of embedded systems. With the development of multimedia and telecommunication technology, the higher level of performance environments is required. Moreover there is some difficulty in improving the performance of an RTOS which is based on a microprocessor. In this paper, we propose a hardware architecture to implement some functions of uC/OS-II as a target RTOS for the purpose of its performance improvement. The proposed architecture for uC/OS-II is implemented and analyzed with the performance comparison.

• Journal of Communications and Networks
• /
• v.13 no.1
• /
• pp.70-76
• /
• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• Journal of Information Processing Systems
• /
• v.8 no.1
• /
• pp.133-144
• /
• 2012

In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.1C
• /
• pp.12-18
• /
• 2008

This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

• International Journal of Naval Architecture and Ocean Engineering
• /
• v.11 no.1
• /
• pp.274-284
• /
• 2019

The control architectures of Chuan Suo (CS) deep submergence rescue vehicle are introduced. The hardware and software architectures are also discussed. The hardware part adopts a distributed control system composed of surface and underwater nodes. A computer is used as a surface control machine. Underwater equipment is based on a multi-board-embedded industrial computer with PC104 BUS, which contains IO, A/D, D/A, eight-channel serial, and power boards. The hardware and software parts complete data transmission through optical fibers. The software part involves an IPC of embedded Vxworks real-time operating system, upon which the operation of I/O, A/D, and D/A boards and serial ports is based on; this setup improves the real-time manipulation. The information flow is controlled by the software part, and the thrust distribution is introduced. A submergence vehicle heeling control method based on ballast water tank regulation is introduced to meet the special heeling requirements of the submergence rescue vehicle during docking. Finally, the feasibility and reliability of the entire system are verified by a pool test.