• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1471-1477
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• 2003

In order to realize the Gbps VPN system, however, newer and more advanced technologies are required to enable wire-rate processing across a wide range of functions and layers. While it is generally accepted that a software soluTion on general-purpose processors cannot scale to process these functionsa wire rate, the KEY POINT is that a software solution on general-purpose processors is the most practical way by which these security allocationscan be developed. Many of these security functions require application layer processing on the content of the packets, and the very nature of application layer software development is characterized by relatively large code size with a high need for portability an flexibility. We have analysed the consideration and specification for realizing Gbps VPN system. from this work. we can obtain a technology of originality.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1851-1856
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• 2013

An XML is widely used for web services, such as SOAP(Simple Object Access Protocol) and REST (Representational State Transfer), and also de facto standard for representing data. Since the XML parser using DOM(Document Object Model) requires a preprocessing task creating a DOM-tree, and then storing it into memory, embedded systems with limited resources typically employ a streaming XML parser without preprocessing. In this paper, we propose a new architecture for the streaming XML parser using an APSearch(Adaptive Parallel Search) on FPGA(Field Programmable Gate Array). Compared to other approaches, the proposed APSearch parser dramatically reduces overhead on the software side and achieves about 2.55 and 2.96 times improvement in the time needed for an XML parsing. Therefore, our APSearch parser is suitable for systems to speed up XML parsing.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.368-376
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• 2005

Multiprocessor architecture becomes increasingly common on real-time systems as computer hardware technology rapidly progresses and the workload of real-time systems increases. However, efficient solutions for many real-time multiprocessor scheduling problems are not known. Hence many researchers apply uniprocessor scheduling algorithms to multiprocessor scheduling or devise new algorithms based on these algorithms. Such algorithms are EDF (Earliest Deadline First), LLF (Least Laxity First), EDF-US[m/(2m-1)], and EDZL (Earliest Deadline Zero Laxity), and comparative studies on them are necessary. In this paper, we show the dominance relation of these algorithms with respect to schedulability, and we prove EDZL strictly dominates EDF. The simulation results show that EDZL has high processor utilization and it causes a small number of preemptions.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1247-1255
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• 2016

The safety and autonomous flight function of micro UAV or drones is crucial to its commercial application. The requirement of own building stable drones is still a non-trivial obstacle for researchers that want to focus on the intelligence function, such vision and navigation algorithm. The paper present a GCS using commercial drone and hardware platforms, and open source software. The system follows modular architecture and now composed of the communication, UI, image processing. Especially, lane-keeping algorithm. are designed and verified through testing at a sports stadium. The designed lane-keeping algorithm estimates drone position and heading in the lane using Hough transform for line detection, RANSAC-vanishing point algorithm for selecting the desired lines, and tracking algorithm for stability of lines. The flight of drone is controlled by 'forward', 'stop', 'clock-rotate', and 'counter-clock rotate' commands. The present implemented system can fly straight and mild curve lane at 2-3 m/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1081-1094
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• 2016

KREONET is a principal national R&E network running by KISTI in Korea. It uniquely provides production research network services for around 200 non-profit research and educational organizations, based on hybrid (IP and non-IP) network infrastructure. However, KREONET is limited to meet various needs of new network services for advanced Science & Technology (S&T) users because its infrastructure is inherently derived form classical hardware-based, fixed and closed environments. So, KREONET-S is designed to provide advanced S&T services to catch up with time-to-research and time-to-collaboration. In this paper, we present a system architecture of KREONET-S based on network infrastructure that consists of data and control planes separately. Furthermore, we propose and describe VDN service which is capable of building a virtual dedicate & bandwidth-guaranteed network for S&T group dynamically. we implement VDN application on KREONET-S and then perform performance analysis for proving that KREONET-S system and VDN application can be a good solutions to cope with new network paradigms for various advanced S&T applications and users.

• Korean Institute of Interior Design Journal
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• v.19 no.1
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• pp.16-26
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• 2010

In recent, as rediscovery of the modern value is developed through the support by the government and the reinterpretation of the traditional culture, a Korean-style house(Hanok) also becomes an object of interest. Among these various viewpoints to see the Korean-style house, the necessity of a new spatial design approach to contain the types and functions of the architectural space of the Hanok appropriate to the modern society is raised which is not a passive approach to preserve the existing cultural assets. Out of the methods of the new spatial design of the Hanok which reflect the paradigm of the times, this study has the purpose to make an approach from the viewpoint of 'Restoration design'. As the 21 st century started, the recycle design whose active discussion and performance is made largely by Europe and Japan can be called a design method in the hardware part which enables continuous adaptive use of a building by applying a new use purpose and method to a building which doesn't use the recycle design or has low efficiency. In that meaning, it can be considered to be a very important architectural activity historically, archltecturally and spatially. Based on the methodological characteristics of the recycle design, this study largely divides the types of recycle into coherent recycle and imagery recycle and dedto s detailed methods of space, consinto ion and material and wardrobe used for each case to analyze the methods of concrete recycle design through the methodological analysis of recycle cases of the existing modern buildings. For the objects of recycle cases of the Hanok made recently based on the design methods acquired here, it was examined how the architectural and spatial characteristics of the Hanok can be reconsinto ed through what kinrecycmethods. The approach of the recycle design is considered to be a cornerstone to show a new architectural and spatial value in the viewpoint of the Hanok existence in modern times.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.4
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• pp.767-773
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• 2000

As computer systems and communication technologies develop rapidly, CSCW(Computer Supported Collaborative Work) system appears nowadays, through which it is available to work on virtual space without any restriction of time and place. Most of CWCS systems depend on a special network and groupware. The systems of graphics and CAD are not so many because they are specified by hardware and application software. In this paper, we propose a web-based collaborative CAD system, which can be jointly worked on Internet WWW being independent from any platforms. It can create and modify 3D objects easily using VRML and Java 3D API, and it can send, print, and store them. The interactive work for designing objects can be also carried out through chatting with each other. This system is executed in the environment of Client/server architecture. Clients connect to the CAD sewer through Java applet on WWW. The server is implemented by Java application, and it consists of three components : connection manager which controls the contact to users, work manager which keeps viewing in concurrency and provides virtual work space sharing with others, and solid modeler which creates 3D object.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.329-334
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• 2014

This paper proposes the hardware architecture of high performance multi-mode 2D forward transform for HEVC which has same number of cycles for processing any type of four TUs and yield high throughput. In order to make the original image which has high pixel and high resolution into highly compressed image effectively, the transform technique of HEVC supports 4 kinds of pixel units, TUs and it finds the optimal mode after performs each transform computation. As the proposed transform engine uses the common computation operator which is produced by analyzing the relationship among transform matrix coefficients, it can process every 4 kinds of TU mode matrix operation with 35cycles equally. The proposed transform block was designed by Verilog HDL and synthesized by using TSMC 0.18um CMOS processing technology. From the results of logic synthesis, the maximum operating frequency was 400MHz and total gate count was 214k gates which has the throughput of 10-Gpels/cycle with the $4k(3840{\times}2160)@30fps$ image.