• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.981-984
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• 1993

During the past decade, several specific hardwares for fast fuzzy inference have been developed. Most of them are dedicated to a specific inference method and thus cannot support other inference methods. In this paper, we present a hardware architecture called KAFA(KAist Fuzzy Accelerator) which provides various fuzzy inference methods and fuzzy set operators. The architecture has SIMD structure, which consists of two parts; system control/interface unit(Main Controller) and arithmetic units(FPEs). Using the parallel processing technology, the KAFA has the high performance for fuzzy information processing. The speed of the KAFA holds promise for the development of the new fuzzy application systems.

• Journal of the Semiconductor & Display Technology
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• 제20권4호
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• pp.151-156
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• 2021

Low-end IoT devices do not have enough computation and memory resources for DNN learning and inference. Integer quantization of real-type neural network models can reduce model size, hardware computational burden, and power consumption. This paper describes the design and implementation of a web-based quantization platform for CNN deep learning accelerator chips. In the web service platform, we implemented visualization of the model through a convenient UI, analysis of each step of inference, and detailed editing of the model. Additionally, a data augmentation function and a management function of files that store models and inference intermediate results are provided. The implemented functions were verified using three YOLO models.

• Progress in Medical Physics
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• 제14권1호
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• pp.20-27
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• 2003

For the treatment of cancer using computer controlled linear accelerator, it is important to ensure that all equipments are operated properly. Therefore, many studies were performed and published on the safe use of radiotherapy machine controlled by computer logic and microprocessor These studies provided methods of preventing accident from software and hardware failure. In Korea, the use of computer controlled linear accelerator has increased over the past 10 years. However, there are no standard protocols for quality assurance (QA) of linear accelerator. In this study, three QA protocols from America, Japan, and Europe were collected and summarized. In addition, agreement and disagreement among the protocols were analyzed. In conclusion, the QA items included in the protocols were similar among the various QA protocols although there were differences in performance frequencies.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제59권3호
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.112-116
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• 1992

In this paper, a fuzzy logic controller(FLC) is designed for the pointing loop of the spin-stabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. The pointing loop of the spin-stabilized platform using FLC has better performance of step responses than a proportional controller in case of same loop hain through the software simulation and the experiment of implemented hardware.

• Journal of Korea Multimedia Society
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• 제19권7호
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• pp.1154-1158
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• 2016

This paper presents a System-On-a-chip for embedded image processing applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2000년도 가을 학술발표논문집 Vol.27 No.2 (3)
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• pp.3-5
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• 2000

고성능의 3차원 그래픽 가속기 설계를 위해서는 어플리케이션, 하드웨어 구조, 수행모델 채택, 설계비용 등의 다양한 고려사항이 요구되고 따라서 각 모델에 따른 사전 시뮬레이션 환경구축은 반드시 필요하다. 이에 본 논문에서는 기본적인 3차원 그래픽 파이프라인 작업을 수행하여 다양한 결과를 보여주는 이식성 높은 시뮬레이션 환경을 제공함으로써 3차원 그래픽 가속하드웨어 세부모듈 설계에 필요한 설계 고려사항을 효과적으로 제시할 수 있게 하였다.

• Journal of Industrial Technology
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• 제11권
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• pp.55-63
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• 1991

This paper presents a design of the accelerate circuit for the conversion of the vector font data into the bit-mapped image. Among the Bezier curve algorithm, the subdivision algorithm gives the good performance and easy hardware implementation. The sequencer is realized by the proprammable gate array and the processing unit is composed of EPLDs and TTL ICs.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제58권10호
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 한국방송∙미디어공학회 2020년도 하계학술대회
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• pp.544-545
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• 2020

본 논문에서는 영상 콘텐츠의 지적재산권 보호를 위하여 딥 러닝을 기반으로 하는 워터마킹 시스템 및 하드웨어 가속기 구조를 제안한다. 제안하는 워터마킹 시스템은 호스트 영상과 워터마크가 같은 해상도를 갖도록 변화시키는 전처리 네트워크, 전처리 네트워크를 거친 호스트 영상과 워터마크를 정합하여 워터마크를 삽입하는 네트워크, 그리고 워터마크를 추출하는 네트워크로 구성된다. 이 중 호스트 영상의 전처리 네트워크와 삽입 네트워크를 하드웨어로 설계한다.