• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.385-389
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• 2003

There are four main components of the CMP process: polishing pad, slurry, elastic supporter, and pad conditioner. The polishing pad is an essential component to the reproducibility of polishing uniformity in CMP process. However, the polishing pad in recently using metal CMP raised the several points of high cost caused by the increase of cycle time and the many usage of slurry. It is necessary to develop the novel polishing pad which would lead the cost reduction by the higher pad life-cycle, minimized cycle time and lower slurry usage. The characteristics of polishing pad were studied on the effects of different sets of the Polishing pad, which can be applied to metal chemical mechanical polishing process for global planarization of multilevel interconnection structure. The main purpose of this experiment is cost reduction by the increase of pad life-time, the decrease of cycle time and the lower usage of slurry through the specific hard porous structured pad design. It is confirmed that the novel polishing pad made the slurry usage decrease to 60% as well as the pad life-time increase twice with the 25% improvement of removal rate. The polishing time could be decreased and it also helped the cycle time to diminish. It can be expected that this results will help both the process throughput and the device yield to be improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.54-57
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• 2001

We studied the characteristics of polishing pad, which can apply STI-CMP process for global planarization of multilevel interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was defected less than 2 on JRlll pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and devise yield.

• Journal of Computing Science and Engineering
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• v.9 no.2
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• pp.51-72
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• 2015

Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.

• Journal of the Korean Society of Physical Medicine
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• v.11 no.1
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• pp.45-52
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• 2016

PURPOSE: The purpose of this study was to determine the effects of balance training on balance pad and sand on balance and gait ability in stroke patients. METHODS: Sixty stroke patients were divided into a Balance Pad group(BPG, N = 20), a Sand group (SG, N = 20) and a Hard Ground group (HGG, N = 20) randomly. The subjects in the Hard Ground group stood in a comfortable position, faced a therapist, then threw a Swiss ball back and forth. They then performed balance training in which they raised and lowered their ankles while facing forward or moved objects from one table to another. The BPG performed same tasks in HGG, on an unstable surface using a balance pad. The SG performed same tasks on sand ground. All groups received training 30min per day, five times per week, for eight weeks. RESULTS: After intervention, all groups showed significant increases balance and gait components. And the BPG and the SG showed significant increase in weight distribution rate, Sway length and BBS compared with the HGG, but there was no significant difference in Cadence, Stride length among three groups. CONCLUSION: According to the results of this study, balance training on unstable surface using balance pad and sand was more effective in improving balance in stroke patients.

• Transactions of the Society of Information Storage Systems
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• v.3 no.3
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• pp.139-143
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• 2007

In recent years new recording media and materials for head-disk interface (HDI) have been developed in order to increase the recording density of storage devices and decrease the cost of production. It is well known that HDI in hard disk drive (HDD) needs high durability and stability. The tribological characteristic of commercialized HDI systems is an important indicator of the HDD reliability. In this study, experimental investigation on the wear coefficient of commercialized hard disk slider pads was performed. The slider was placed on top of a hard disk and allowed to slide for a set distance. The wear of the pads was measured after the sliding tests. The result showed that the micro-bumps in commercialized HDD have extremely low wear coefficient of $10^{-11}$. The results of this work may be used for further development of the HDI technology for HDD.

• Archives of Plastic Surgery
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• v.37 no.1
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• pp.31-36
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• 2010

Purpose: The primary goal of palatoplasty is to enable normal speech with harmonious growth of face. Some children who had palatoplasty display typical findings of transverse maxillary deficiency requiring orthodontic widening of the maxilla. Levi (2009) described a cleft palate repair coupled with pedicled buccal fat pad flaps to cover bone exposed areas of the hard palate. Hence we report clinical experiences of cleft palate repair using pedicled buccal fat pad flap. Methods: Four Veau class II and a Veau class I cleft palate patients underwent palatoplasty with buccal fat pad flap by single surgeon from April 2009 to August 2009. Two patients received 2-flap palatoplasty and three patients 1-flap palatoplasty, respectively. After the cleft palate repair, sharp mosquito scissors was placed in the superior buccal sulcus just lateral to the maxillary tuberosity and inserted directly through the mucosa resulting in buccal fat pad extrusion. The elevated flap was moved to cover mucoperiosteal defect in hard palatal area. Results: Five patients underwent primary palatoplasty using buccal fat pad flap. Flap harvest and inset took on average 9 minutes per flap. Mucosal epithelization took 18 days on average. No patients had complications related to the buccal fat pad flap. Conclusion: Buccal fat pad pedicled flap has significant potential to function as an added vascularized tissue layer in cleft palate repair and we can expect better growth of maxilla with this method although longer duration of follow-up was unavailable.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.7
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• pp.568-574
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• 2000

We have been optimized tungsten(W) plug CMP(chemical mechanical polishing) characteristics using two different kinds of component of slurry and two different kinds of pad which have different hardness. The comparison of oxide film roughness on around W plug after polishing has been carried out. And W plug recess for consumable sets and dishing effect at dense area according to the rate of over-polishing has been investigated. Also the analysis of residue on surface after cleaning have been performed. As a experimental result we have concluded that the consumable set of slurry A and hard pad was good for W plug CMP process. After decreasing the rate of chemical reaction of silica slurry and adding two step buffering we could reduce the expanding of W plug void however we are still recognizing to need a more development for those kinds of CMP consumables.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.4
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• pp.183-188
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• 2003

Particulate contamination is known to be a significant cause of failures of removable storage media. In this work, the effect of particles on the surface damage of removable hard disk media was investigated. The particles of different materials and size were introduced to the Head Disk Interface (HDI) using a particle injection system. It was round that the particles of particulate size and property serious damaged the media. This study showed that cleaning pad is effective for reducing particle contamination, except fer the particles of specific size and property. As a means to remove the particles of specific sire. the concept of using a stepped taper at the leading edge of the slider is proposed.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.11
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• pp.46-56
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• 1996

Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.