• Transactions of the Korean Society of Automotive Engineers
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• v.8 no.3
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• pp.190-197
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• 2000

A graphic vehicle modeling pre-processing program and a visualization post-processing program have been developed for AutoDyn7, which is a special program for vehicle dynamics. The Rapid-App for GUI(Graphic User Interface) builder and the Open Inventor for 3D graphic library have been employed to develop these programs in Silicon Graphics workstation. A Graphic User Interface program integrates vehicle modeling pre-processor, AutoDyn7 analysis processor, and visualization post-processor. In vehicle modeling pre-processor, vehicle hard point data for a suspension model are automatically converted into multibody vehicle system data. An interactive graphics capabilities provides suspension modeling aides to verify user input data interactively. In visualization post-processor, vehicle virtual test simulation results are animated with virtual testing environments.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.1
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• pp.1-9
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• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.443-445
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• 1990

In this paper, a high speed graphic processor module with a real-time processing capability is proposed, where the module is design to be compatible to the standard VME bus and consists of TMS34010 Graphic processor, TMS44C251 frame buffer, 512KB system memory and BT101 digital to analog converter. The proposed graphic module is implemented and tested in real-time via experiments with an integrated system with other VME modules.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.72-82
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• 2002

This paper presents the design technology of a Graphic Generator which drives the embedded aircraft display equipments such as HUD(Head-Up Display) and MFD (Multi-Function Display) those provide pilot with the most important mission information. The main issue of this design is how we can implement the real-time embedded graphic generator using a general purpose processor as a substitute for the obsolete the production of specific graphic processor in the military market. So we proposed two kinds of method that one is a software solution so called graphic kernel system, interpreting the display file, controlling the graphic system and pre-processing graphic primitives, the other is a hardware solution so called graphic engine, interpreting passed commands through the graphic kernel system, post-processing the looping calculation taking much of time as implemented by software. We have tested and verified the functionalities and the required performance of Graphic Generator.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.485-490
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• 2017

In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.6
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• pp.7-14
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• 1998

A graphic user interface program for the design of vehicle suspension system is developed in this work. Graphic templates are designed by using a graphic language and a library and given to users for interactive data input. Several suspension types are graphically given, and the information of hard points can be directly provided on the graphic templates by users. The information is saved in a data structure which can be efficiently accessed, and transformed into another data format. The data transformation is for the interface to an analyzer by which suspension design characteristics can be calculated.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.507-512
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• 2014

Recently, Distributed computing processing begins using both CPU(Central processing unit) and GPU(Graphic processing unit) to improve the performance to overcome darksilicon problem which cannot use all of the transistors because of the electric power limitation. There is an integrated graphics processor that CPU and GPU share memory and Last level cache(LLC). But, There is no LLC access rules between CPU and GPU, so if GPU and CPU processes run together at the same time, performance of both processes gets worse because of the contention on the LLC. This Paper gives evidence to prove the need of the Cache Partitioning and is mentioned about the cache partitioning design using page coloring to allocate the L3 Cache space only for the GPU process to guarantee GPU process performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.802-807
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• 1990

In this thesis, we represent the study on the design and implementation of the hangul graphic board which generate bit map font data from the boundary information of korean or chines fonts. The implemented graphic board consists of a TMS34010 Graphic System Processor (GSP) and two TMS320C25 Digital Signal Processor (DSP), and there is shared memory which consists of two memory blocks with same address for which is possible parallel processing between two processors. And in using DSP, we propose an efficient algorithm for calculation of Bezier curve which require much times to calculate bit map data font from the boundary information.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.85-95
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• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.37-47
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• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.