• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.12-14
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• 2001

In this paper, three dimensional Equivalent Magnetic Circuit Method(3-D EMCN method), a numerical analysis method which supplements to magnetic equivalent circuit adding numerical technique, is proposed for analysis Optical Pickup Actuator. [3] This method provides better characteristics both in precision of the analysis and in computation time than other analysis method such as three-dimensional Finite Element Method. RCS Niching Genetic Algorithm are used for optimal design.

• ETRI Journal
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• v.45 no.4
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• pp.690-703
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• 2023

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

• Nuclear Engineering and Technology
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• v.55 no.6
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• pp.2125-2138
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• 2023

The printed circuit heat exchanger (PCHE) with airfoil fins has the benefits of high compactness, high efficiency and superior heat transfer performance. A novel multi-objective optimization approach is presented to design the airfoil fin PCHE in this paper. Three optimization design variables (the vertical number, the horizontal number and the staggered number) are obtained by means of dimensionless airfoil fin arrangement parameters. And the optimization objective is to maximize the Nusselt number (Nu) and minimize the Fanning friction factor (f). Firstly, in order to investigate the impact of design variables on the thermal-hydraulic performance, a parametric study via the design of experiments is proposed. Subsequently, the relationships between three optimization design variables and two objective functions (Nu and f) are characterized by an improved particle swarm optimization-backpropagation artificial neural network. Finally, a multi-objective optimization is used to construct the Pareto optimal front, in which the non-dominated sorting genetic algorithm II is used. The comprehensive performance is found to be the best when the airfoil fins are completely staggered arrangement. And the best compromise solution based on the TOPSIS method is identified as the optimal solution, which can achieve the requirement of high heat transfer performance and low flow resistance.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.1943-1944
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• 2006

"Dynamic Neural Unit"(DNU) based upon the topology of a reverberating circuit in a neuronal pool of the central nervous system. In this thesis, we present a genetic DNU-control scheme for unknown nonlinear systems. Our methodis different from those using supervised learning algorithms, such as the backpropagation (BP) algorithm, that needs training information in each step. The contributions of this thesis are the new approach to constructing neural network architecture and its trainin

• International Journal of Control, Automation, and Systems
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• v.4 no.1
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• pp.96-104
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• 2006

We propose a path planning method to improve the productivity of AOI (automated optical inspection) machines in PCB (printed circuit board) assembly lines. The path-planning problem is the optimization problem of finding inspection clusters and the visiting sequence of cameras to minimize the overall working time. A unified method is newly proposed to determine the inspection clusters and visiting sequence simultaneously. We apply a hybrid genetic algorithm to solve the highly complicated optimization problem. Comparative simulation results are presented to verify the usefulness of the proposed method.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2484-2486
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• 2004

"Dynamic Neural Unit"(DNU) based upon the topology of a reverberating circuit in a neuronal pool of the central nervous system. In this thesis, we present a genetic DNU-control scheme for unknown nonlinear systems. Our method is different from those using supervised learning algorithms. such as the back propagation (BP) algorithm, that needs training information in each step. The contributions of this thesis are the new approach to constructing neural network architecture and its trainin.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Proceedings of the KAIS Fall Conference
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• 2006.05a
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• pp.311-315
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• 2006

"Dynamic Neural Unit"(DNU) based upon the topology of a reverberating circuit in a neuronal pool of the central nervous system. In this thesis, we present a genetic DNU-control scheme for unknown nonlinear systems. Our methodis different from those using supervised learning algorithms, such as the backpropagation (BP) algorithm, that needs training information in each step. The contributions of this thesis are the new approach to constructing neural network architecture and its trainin

• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.217-220
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• 2004

'Dynamic Neural Unit'(DNU) based upon the topology of a reverberating circuit in a neuronal pool of the central nervous system. In this thesis, we present a genetic DNU-control scheme for unknown nonlinear systems. Our methodis different from those using supervised loaming algorithms, such as the backpropagation (BP) algorithm, that needs training information In each step. The contributions of this thesis are the new approach to constructing neural network architecture and its trainin.