• ETRI Journal
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• 제31권2호
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1670-1676
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• 2014

This paper presents the modeling of Single Electron Transistor (SET) based on Physical model of a device and its equivalent circuit. The physical model is derived from Schrodinger equation. The wave function of the electrode is calculated using Hartree-Fock method and the quantum dot calculation is obtained from WKB approximation. The resulting wave functions are used to compute tunneling rates. From the tunneling rate the current is calculated. The equivalent circuit model discuss about the effect of capacitance on tunneling probability and free energy change. The parameters of equivalent circuit are extracted and optimized using genetic algorithm. The effect of tunneling probability, temperature variation effect on tunneling rate, coulomb blockade effect and current voltage characteristics are discussed.

• 산업경영시스템학회지
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• 제29권1호
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• pp.63-71
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• 2006

In this paper, we consider a planning problem arising from printed circuit board manufacturing industries. Given a set of several types of PCBs, component feeders and surface mounting machines in series in a PCB assembly line, the problem is to define the feeder allocation and job sequence with the objective of minimizing the total operation time of the line. We formulate the problem as a mathematical model. And, the problem is proven to be NP-hard, so a genetic algorithm is developed. Finally, we give test results to evaluate the performance of the genetic algorithm.

• 한국컴퓨터정보학회논문지
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• 제7권3호
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• pp.42-48
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• 2002

배치(Placement)는 VLSI 회로의 physical design에서 중요한 단계로서 회로의 성능을 최대로 하기 위하여 회로 모듈의 집합을 배치시키는 문제이며, 배치 문제에서 최적의 해를 얻기 위해 클러스터 성장(cluster growth), 시뮬레이티드 어닐링(simulated annealing; SA), ILP(integer linear programming)등의 방식이 이용된다. 본 논문에서는 배치 문제에 대하여 유전자 알고리즘(genetic algorithm; GA)을 이용한 해 공간 탐색(solution space search) 방식을 제안하였으며, 제안한 방식을 시뮬레이티드 어닐링 방식과 비교, 분석하였다.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 한국정보통신학회논문지
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• 제14권1호
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• pp.177-182
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• 2010

포워드 컨버터는 광범위하게 사용되는 파워공급기 중의 하나이다. 본 논문은 부하가 다양하게 변동하는 환경에서 출력 전압의 변동을 최소화하는 포워드 컨버터의 최적회로 소자 값을 구하기 위한 파라메터 동조방법을 제시한다. 위상여유의 개념을 사용하는 기존의 방법은 최적의 위상여유를 통해 출력 전압 응답에서 부분적인 성능 개선이 이루어지도록 확장되었다. 이를 위해서 위상여유를 동조 파라메터로 두고 유전자 알고리즘을 사용하여 최적화하였다. 다음으로 회로 소자 값들을 동조 파라메터로 직접 선택하고, 역시 유전자 알고리즘으로 최적화하여 포워드 컨버터의 출력 전압 제어에서 매우 개선된 성능을 갖도록 하였다.

• 대한기계학회논문집A
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• 제38권11호
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• pp.1215-1220
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• 2014

회로차단기에서 가장 중요한 성능은 전기시스템의 이상전류를 신속하게 차단하는 것이다. 이러한 차단시간은 조작기구의 동적 특성에 의한 영향을 받는다. 따라서 회로차단기의 차단시간 단축을 위해서는 조작기구의 최적화가 이루어져야 한다. 본 논문의 가스회로차단기의 조작기는 스프링으로 구동되며 여러 개의 Latch 로 구성되어있다. Latch 들의 상대적 위치와 길이로 정의된 각 설계변수의 차단시간에 대한 영향을 분석하고 이 결과를 통해 설계변수를 선정하여 ADAMS 와 VisualDOC 의 연동을 통해 최적화를 수행하였다. Latch 들의 최적화를 통해 약 22.5% 개극시간을 향상을 확인하였다.

• 동력기계공학회지
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• 제13권4호
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• pp.68-73
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• 2009

The mathematical model has a different response character with the real system because this mathematical model has the modeling errors and the imprecise value of system's parameters. Therefore to find the value of system parameters as possible as near by real value in the model is necessary to design the controlled system. This study concern about the identification method to estimate the parameter for the magnetic bearing system with RCGA(Real Coded Genetic Algorithm). Firstly, we will get the mathematical model from the current amplifier circuit and the magnetic bearing system. Secondly we will get the step response data in this circuit and system. Finally, we will estimate the unknown parameter's value from the data.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권5호
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• pp.325-331
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• 2004

The multiobjective optimization (MO) problem usually includes the conflicting objectives and the use of conventional optimization algorithms for MO problem does not so good approach to obtain an effective optimal solution. In this paper, genetic algorithm (GA) as an effective method is used to solve such MO problem of brushless DC motor (BLDCM). 3D equivalent magnetic circuit network (EMCN) method which enables us to reduce the computational burden is also used to consider the 3D structure of BLDCM. In order to effectively obtain a set of Pareto optimal solutions in MO problem, ranking method proposed by Fonseca is applied. The objective functions are decrease of cogging torque and increase of torque respectively. The airgap length, teeth width and magnetization angle of PM are selected for the design variables. The experimental results are also shown to confirm the validity of the optimization results.