• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.4
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• pp.93-102
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• 1995

The purpose of this paper is to analyze the streaming electrification mechanism (SEM) generated in UHV transformer. This experiment used Couette Charger and interpreted the mechanism hydromechanically and electromagnetically. This work estimated the turbulent core density ($\rho$o) by measuring the short circuit current (isc) and the open circuit voltage (νoc) generated in Couette Charger and also studied the changes of the short circuit (isc), the open circuit voltage (νoc), the turbulent core density ($\rho$o) and the conductivity ($\sigma$) with adding BTA to restrain streaming electrification. as a result adding BTA increased the conductivity of oil and decreased the turbulent core density($\rho$o).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.3
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• pp.547-555
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• 2007

In order to transmit energy generated through the stator winding of a doubly-fed induction generator (DFIG), we need to synchronize the generated voltage vector with the grid voltage vector. However, the existing synchronization methods work only when the encoder is installed at a specific position and equivalent constant is precise. In order to solve this problem, a new synchronization method has been proposed and a way of applying the method to existing doubly-fed induction generator control algorithm has been also proposed. The validities of the methods proposed were verified by using a prototype converter for a 1.5MW-class doubly-fed induction generator and experimental results showed the validity of that against variation of an encoder positions, generator parameters, and grid voltages.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1597-1599
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• 2001

In this paper, two types of surge voltage generated in the only operation of capacitor bank composed of paralleled multi-modules are analyzed and also studied to suppress those. The surge voltage can give malfuction to the operation of capacitor bank and destroy the expensive components at the worst. The conditions and causes of surge voltage generation and the countermeasure for suppression are presented.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.17-20
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• 2002

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4A to 814A with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ The oxide charge state of traps generated by the stress high voltage contain either a positive or negative charge.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1904-1906
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• 1996

Transient voltage distribution tests are carried out to evaluate effects of a high frequency oscillating voltage generated in a superconducting magnet as a result of the arc discharge extinction. Especially, the effects of temperature and conduction state of the magnet conductor on surge behavior are carefully investigated. Based on the results of simulation tests, it is shown that internal voltage waveforms are influenced by its transmission along the superconducting wire and reflection at the terminal and that attenuation process of the waveforms depends considerably on the conductor resistance which decreases with lowering the temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Transactions on Electrical and Electronic Materials
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• v.4 no.6
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Journal of Environmental Science International
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• v.32 no.3
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• pp.197-204
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• 2023

This study aims to inactivate Artemia sp. (Zooplankton) in ballast water through the dielectric barrier discharge (DBD) plasma process. The DBD plasma process has the advantage of enabling direct electric discharge in water and utilizing chemically active species generated by the plasma reaction. The experimental conditions for plasma reaction are as follows; high voltage of 9-22 kV, plasma reaction time of 15-600 s, and air flow rate of 0.5-5.5 L/min. The results showed that the optimal experimental conditions for Artemia sp inactivation were 16 kV, 60 s, 2.5 L/min, respectively. The concentrations of total residual oxidants and ozone generated by plasma reaction increased with an increase of in voltage and reaction time, and the concentration of generated air did not increase above a certain amount.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.1
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• pp.18-23
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• 2010

As the increasing of Non-linear load, we have been growing interest for the harmonics. Harmonics has been focused on the current component rather than voltages. Voltage harmonics can be mainly generated at the PCC with non-linear load and act on voltage unbalance. Voltage harmonics can be enlarged at the capacitor with low impedance as frequency increases. Capacitor is basically used for the power-factor compensation and sometimes as the passive filter. Small voltage of low-order acts on quite a few at the capacitor by the current increase. Capacitor has easily fall under by harmonic components. In this paper, we measured the magnitude and phase angle of asymmetrical voltage with harmonics components at the PCC and calculated with the same condition. we concluded that voltage harmonics of higher order increase each current component but have a little effect on capacitor rating.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.11
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• pp.1174-1177
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• 2012

In voltage measurement by using voltage divider with series resistors, error is generated caused by the variation of resistance. In order to reduce these errors, the hardware cost tends to increase in the previous works. In the proposed method, three resistors are used for the voltage divider of which the organization is adjusted by using switches. Three voltages are measured and the ratio of resistance is calculated based on the measured voltages. Since the resistance ratio is calculated by measuring voltages and additional hardware cost is minimal, the voltage can be measured with high accuracy and low cost. Experimental results show that the mean absolute error is 12.1 mV when the input voltage ranges from 5 V to 50 V.