• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.598-599
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• 2017

In motor application, High efficiency is important. So Design engineer select small gate resistor for lower switching. But There is side effect with small gate resistor. It makes large dv/dt and system request large EMI filter. It makes price increase. This paper introduce about gate drive IC which have solution both of lower loss and EMI issue.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.542-545
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• 2002

This paper deals with the optimization inverter design and minimization Conduced EMI noise by customizing IPM(Intelligent Power Module). Generally, In case of IPM, we realized that the trade-off relation between switching loss and spike voltage. Higher gate resistor causes tile lower spike voltage and the higher turn-off switching loss. But we know that the life cycle of inverter and the susceptibility of noise, so we optimized the gate resistor. Proposed method is that optimized the gate resistor suitable for the inverter and motor. The simulation and experimental results show that the spike voltage and Conduced EMI noise can be reduced without the additional circuit.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.2
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• pp.111-121
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• 1999

This paper deals with an active gate drive (AGD) technolo밍T for high power IGBTs. It is based on an optimal c combination of several requirements necessmy for good switching performance under hard switching conditions, The s scheme specifically combines together the slow drive requirements for low noise and switching stress and the fast driver requirements for high speed switching and low switching energy loss The gate drive can also effectively dampen oscillations during low cunent turnlongrightarrowon transient in the IGBT, This paper looks at the conflicting requirements of the c conventional gate dlive circuit design and the experimental results show that the proposed threelongleftarrowstage active gate dlive t technique can be an effective solution.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.4
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• pp.313-320
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• 2003

This paper deals with the optimal design of a elevator inverter system based on the customized IPM. The proposed method reduces dv/dt and di/dt, which resulted in the minimized conducted EMI noise without an additional circuitry. It only optimizes the value of gate resistor in the IGBT embedded in the IPM. In order to optimize the customized IPM to a elevator system, we simulated and measured the spike voltage and the motor surge voltage including the temperature variation due to the switching losses at the IPM case and heat-sink. As a result, thanks to the optimized value of the gate resister in the IPM, the conducted EMI noise is reduced approx. 5∼10 [dB$\mu$V] in a particular frequency domain.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.325-328
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• 2002

In this paper. we propose a floating resistor with positive and negative resistance operating at lower supply voltages. The circuit uses only two transistors between the supply voltages. which enable to operate it at low supply voltages. Moreover. the circuit uses fewer number of transistors compared to the reported work. The gate terminal is used in this circuit for the current addition/subraction at the terminals of resistor. The characteristic of the proposed circuit is verified using HSPICE for the power supply +/-1.5V.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.759-762
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• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.2
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• pp.40-45
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• 1974

It is indicated that in SCR the anode current can be controlled by ajusting the gate voltage when the magnitude of anode current lies in the range of 10-2 to 10-3 Amperes. This fact is applied to make a simple sinusoidal oscillator circuit which has the negative resistance characteristics in its gate circuit by inserting a proper resistor into its cathode circuit.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1402-1408
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• 2015

A MOSFET's gate driver based on magnetic coupling is investigated. The gate driver can meet the demands in applications for wide range of duty cycles and high frequency. Fully galvanic isolation can be realized, and no auxiliary supply is needed. The driver is insensitive to the leakage inductor of the isolated transformer. No gate resistor is needed to damp the oscillation, and thus the peak output current of the gate driver can be improved. Design of the driving transformer can also be made more flexible, which helps to improve the isolation voltage between the power stage and the control electronics, and aids to enhance the electromagnetic compatibility. The driver's operation principle is analyzed, and the design method for its key parameters is presented. The performance analysis is validated via experiment. The disadvantages of the traditional magnetic coupling and optical coupling have been conquered through the investigated circuit.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.