• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.187-187
• /
• 2012

Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

• 한국수소및신에너지학회논문집
• /
• 제15권4호
• /
• pp.317-323
• /
• 2004

We fabricated a MISFET using Pd/NiCr gate for the detecting of hydrogen gas in the air and investigated its electrical characteristics. To improve stability and high concenntration sensitivity and remove the blister generated by the penetration of hydrogen atoms Pd/NiCr catalyst gate metal are used as dual gate. To reduce the gate drift voltage caused by the inflow of hydrogen, the gate insulators of sensing and reference FFET were constructed with double insulation layers of silicon dioxide and silicon nitride. The hydrogen response of MISFET were amplified with the difference of gate voltages of both MISFET. To minimize the drift and the noise, we used a OP177 operational amplifier. The sensitivity of the Pd/NiCr gate MISFET was lower than that of Pd/Pt gate MISFET, but it showed good stability and ability to detect high concentration hydrogen up to 1000ppm.

• Design & Manufacturing
• /
• 제15권1호
• /
• pp.1-7
• /
• 2021

The position of the gate is one of the important factors for optimal injection molding. This is because inappropriate gate positions cannot fill the cavity uniformly, which can lead to defects such as contraction. In this study, CAE was performed on hot runner injection molding of the washing machine base and plasticity was compared by changing gate position from existing gate position. A total of two alternatives have been applied to compare the plasticity of the washing machine base according to its optimal gate position. The gate position of the improved molds and the gate position of the current mold is analyzed by injection molding analysis. The results of the fill time, the pressure at V/P switchover, clamping force, and deflection were compared. In washing machine base injection molding, the deflection was reduced by about 3.76% in the improved mold 2. In improved mold 1, the fill time during injection molding was reduced by 3.32% to enable uniform charging, and the clamping force was reduced by 31.24%. We have confirmed that the position of the gate can change the charging pressure and the clamping force and affect the quality and cost savings of the molded product.

• 대한전자공학회논문지SD
• /
• 제39권5호
• /
• pp.1-7
• /
• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Transactions on Electrical and Electronic Materials
• /
• 제9권1호
• /
• pp.6-11
• /
• 2008

In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

• 한국전자통신학회논문지
• /
• 제14권1호
• /
• pp.87-96
• /
• 2019

유기 박막 트랜지스터 (OTFT) 백플레인을 이용한 유연한 유기 발광 다이오드 (OLED) 디스플레이가 연구되고 있다. OLED 디스플레이의 구동을 위해서 게이트 드라이버가 필요하다. 저온, 저비용 및 대 면적 인쇄 프로세스를 사용하는 디스플레이 패널의 내장형 게이트 드라이버는 제조비용을 줄이고 모듈 구조를 단순화한다. 이 논문에서는 유연한 OLED 디스플레이 패널의 내장형 게이트 드라이버 제작을 위하여 OTFT를 사용한 의사 CMOS (pseudo complementary metal oxide semiconductor) 로직 게이트를 구현한다. 잉크젯 인쇄형 OTFT 및 디스플레이와 동일한 프로세스를 사용하여 유연한 플라스틱 기판 상에 의사 CMOS 로직 게이트가 설계 및 제작되며, 논리 게이트의 동작은 측정 실험에 의해 확인된다. 최대 1 kHz의 입력 신호 주파수에서 의사 CMOS 인버터의 동작 결과를 통하여 내장형 게이트 드라이버의 구현 가능성을 확인하였다.

• 전기전자학회논문지
• /
• 제22권2호
• /
• pp.484-487
• /
• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• 센서학회지
• /
• 제16권4호
• /
• pp.313-318
• /
• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• Progress in Superconductivity
• /
• 제13권1호
• /
• pp.47-51
• /
• 2011

Mono-atomic-layer graphene is an interesting system for studying the relativistic carrier transport arising from a linear energy-momentum dispersion relation. An easy control of the carrier density in graphene by applying an external gate field makes the system even more useful. In this study, we measured the Josephson current in a device consisting of mono-layer graphene sheet sandwiched between two closely spaced (~300 nm) aluminum superconducting electrodes. Gate dependence of the supercurrent in graphene Josephson junction follows the gate dependence of the normal-state conductance. The gate-tunable and relatively large supercurrent in a graphene Josephson junction would facilitate our understanding on the weak-link behavior in a superconducting-normal metal-superconducting (SNS) type Josephson junction.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2009년도 춘계학술대회 논문집
• /
• pp.1943-1950
• /
• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.