• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.15-18
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• 한국전기전자재료학회논문지
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• 제36권6호
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• pp.588-593
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• 2023

The advantage of OTFT technology is that large-area circuits can be manufactured on flexible substrates using a low-cost solution process such as inkjet printing. Compared to silicon-based inorganic semiconductor processes, the process temperature is lower and the process time is shorter, so it can be widely applied to fields that do not require high electron mobility. Materials that have utility as electrode materials include carbon that can be solution-processed, transparent carbon thin films, and metallic nanoparticles, etc. are being studied. Recently, a technology has been developed to facilitate charge injection by coating the surface of the Al electrode with solution-processable titanium oxide (TiOx), which can greatly improve the performance of OTFT. In order to commercialize OTFT technology, an appropriate method is to use a complementary circuit with excellent reliability and stability. For this, insulators and channel semiconductors using organic materials must have stability in the air. In this study, carbon-doped Mo (MoC) thin films were fabricated with different graphite target power densities via unbalanced magnetron sputtering (UBM). The influence of graphite target power density on the structural, surface area, physical, and electrical properties of MoC films was investigated. MoC thin films deposited by the unbalanced magnetron sputtering method exhibited a smooth and uniform surface. However, as the graphite target power density increased, the rms surface roughness of the MoC film increased, and the hardness and elastic modulus of the MoC thin film increased. Additionally, as the graphite target power density increased, the resistivity value of the MoC film increased. In the performance of an organic thin film transistor using a MoC gate electrode, the carrier mobility, threshold voltage, and drain current on/off ratio (I_on/I_off) showed 0.15 cm²/V·s, -5.6 V, and 7.5×10⁴, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.348-348
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• 2011

Carbon nanotube (CNT) field effect transistors and sensors use CNT as a current channel, of which the resistance varies with the gate voltage or upon molecule adsorption. Since the performance of CNT devices depends very much on the CNT/metal contact resistance, the CNT/electrode contact must be stable and the contact resistance must be small. Depending on the geometry of CNT/electrode contact, it can be categorized into the end-contact, embedded-contact (top-contact), and side-contact (bottom-contact). Because of difficulties in the sample preparation, the end-contact CNT device is seldom practiced. The embedded-contact in which CNT is embedded inside the electrode is desirable due to its rigidness and the low contact resistance. Fabrication of this structure is complicated, however, because each CNT has to be located under a high-resolution microscope and then the electrode is patterned by electron beam lithography. The side-contact is done by depositing CNT electrophoretically or by precipitating on the patterned electrode. Although this contact is fragile and the contact resistance is relatively high, the side-contact by far has been widely practiced because of its simple fabrication process. Here we introduce a simple method to embed CNT inside the electrode while taking advantage of the bottom-contact process. The idea is to utilize a eutectic material as an electrode, which melts at low temperature so that CNT is not damaged while annealing to melt the electrode to embed CNT. The lowering of CNT/Au contact resistance upon annealing at mild temperature has been reported, but the electrode in these studies did not melt and CNT laid on the surface of electrode even after annealing. In our experiment, we used a eutectic Au/Al film that melts at 250$^{\circ}C$. After depositing CNT on the electrode made of an Au/Al thin film, we annealed the sample at 250$^{\circ}C$ in air to induce eutectic melting. As a result, Au-Al alloy grains formed, under which the CNT was embedded to produce a rigid and low resistance contact. The embedded CNT contact was as strong as to tolerate the ultrasonic agitation for 90 s and the current-voltage measurement indicated that the contact resistance was lowered by a factor of 4. By performing standard fabrication process on this CNT-deposited substrate to add another pair of electrodes bridged by CNT in perpendicular direction, we could fabricate a CNT cross junction. Finally, we could conclude that the eutectic alloy electrode is valid for CNT sensors by examine the detection of Au ion which is spontaneously reduced to CNT surface. The device sustatined strong washing process and maintained its detection ability.

• 전기전자학회논문지
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• 제22권2호
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• pp.488-490
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• 2018

본 연구에서는 급격한 스위칭 특성을 달성하기 위해 싱글단일-게이트 실리콘 채널에서 전하 캐리어의 양의 피드백을 이용하는 새롭게 설계된 피드백 전계 효과 트랜지스터를 제안한다. 에너지 밴드 다이어그램, I-V 특성, 문턱전압 기울기 및 on/off 전류 비는 TCAD 시뮬레이터를 이용하여 분석한다. 피드백 전계 효과 트랜지스터의 중요한 특징 중 하나인 히스테리시스의 특성을 보기 위해 게이트 절연막 물질과 게이트 전극물질을 변경하여 시뮬레이션을 진행했다. 이러한 특성변화는 피드백 전계효과 트랜지스터의 문턱전압 ($V_{TH}$)을 변화시켰고, 메모리 윈도우 폭이 작아지는 현상을 보였다.

• 마이크로전자및패키징학회지
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• 제10권2호
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• pp.49-54
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• 2003

본 연구에서는 Pt/SrBi$_2$Ta$_2$O$_{9}$(SBT)/Si (MFS)와 Pt/SBT/Pt (MFM) 각각의 구조에서 수소 열처리에 의한 SBT박막의 물리, 전기적 영향에 대해 연구하였다. SBT 박막의 미세구조 및 전기적 특성은 수소 열처리 후에 SBT 박막의 손상으로 열화된다. 특히, Pt 전극에 의한 SBT 박막의 열화 현상을 연구하기 위해 각각 Si 와 Pt 위에 SBT 를 증착하여 같은 조건으로 열처리를 하였다. XRD, XPS, P-V, C-V 측정을 통해 Pt 전극 없이 SBT자체로도 수소 열처리 후에 열화 됨을 확인 할 수 있었다. 또한, 수소 열화현상이라고 하는 촉매 반응으로 SBT 열화 현상이 Pt로 가속화되었다. 이러한 현상을 방지하기 위해서 새로운 Ir 전극을 제안하여 $Ir/IrO_2/SBT/IrO_2$ 구조에서의 수소 열처리 전후 및 회복 열처리를 통해 SBT 박막의 전기적 특성을 연구하였다. P-V측정을 통해 SBT박막을 이용한 MFM구조에서 Ir이 열화 방지용 전극 물질로의 활용 가능성을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1115-1118
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• 2006

Using a thermally-crosslinkable organosiloxane-based organic-inorganic hybrid material, solution processable gate dielectric layer for organic thin-film transistors (OTFTs) have been fabricated. The hybrid dielectrics are synthesized by the sol-gel process, followed by the heat-treatment at $190{\bullet}\;.{\bullet}$ To investigate the electrical property of hybrid dielectric, leakage current behavior and capacitance were measured. To fabricate coplanar-type OTFTs, Au/Cr electrode was deposited onto the heavily doped silicon substrate with the organic-inorganic hybrid dielectric layer and then ${\alpha},{\omega}-dihexylquaterthiophene$ was drop-cast between source and drain electrical performance of the fabricated transistor.

• 마이크로전자및패키징학회지
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• 제30권3호
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• pp.73-77
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• 2023

본 연구에서는 서로 다른 강유전성 물질을 활용하여 Multi-level FeRAM (Ferroelectrics random access memory) 소자에 대한 구조를 제시하였으며, 이를 검증하기 위해 Simulation을 통한 C-V 분석을 수행하였습니다. Multi-level 소자를 구현하기 위해 두 가지 서로 다른 물성을 가진 강유전체를 동일한 하부 전극 위에 나란히 증착하고, 이후 게이트 전극을 위에 올린 MFM (Multi-Ferroelectric Material) 구조를 제안하였습니다. 두 강유전체가 서로 다른 전압 조건에서 분극 현상 (Polarization)을 나타내는 것을 바탕으로, 두 개의 물질 중 한 개만 polarization 되었을 때와 두 개 모두 polarization 되었을 때의 상황을 C-V peak 분석을 통해 확인하여 Multi-level 동작을 구현할 수 있음을 확인하였습니다. 더불어, 제시한 구조를 반도체 제조 공정을 활용하여 구현하는 방법을 공정 simulation을 통해 검증하였습니다. 이러한 결과는 하나의 메모리 셀에서 여러 상태 값을 저장할 수 있음을 의미하며, 이는 메모리의 집적도를 크게 향상시킬 수 있는 새로운 구조체로서의 가능성을 의미합니다.

• 전기전자학회논문지
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• 제22권1호
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• pp.209-212
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• 2018

본 논문에서는 P(VDF-TrFE)유기물 강유전체 기반 metal-ferroelectric-metal (MFM) capacitor 와 차세대 반도체 물질인 질화갈륨 반도체를 활용한 네거티브 커패시턴스 전계효과 트랜지스터를 제작 및 분석 하였다. 27 nm의 두께의 P(VDF-TrFE) MFM 커패시터의 분극지수는 4 MV/cm에서 $6{\mu}C/cm^2$ 값을 나타내었으며 약 65 ~ 95 pF의 커패시턴스 값을 나타내었다. 강유전체의 커패시턴스와 전계효과 트랜지스터의 커패시턴스 매칭을 분석하기 위해 제작된 P(VDF-TrFE) MFM 커패시터는 GaN 전계효과 트랜지스터의 게이트 전극에 집적화 되었으며 집적화되기 전 104 mV/dec 의 문턱전압 이하 기울기에서 82 mV/dec 값으로 개선된 효과를 보였다.