• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.904-905
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• 2008

In this paper, a novel 60kV, 300A, 3kHz pulsed power supply based on IGBT stacks is proposed. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and 15kW series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 830VDC, 300A pulses. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is important of series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.357-360
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• 2003

In this paper, we designed 4.5kV/1.5kA IGCT devices. GCT thyristor has many superior characteristics compared with GTO thyristor, for examples; snubberless turn-off capability, short storage time, high turn-on capability, small turn-off gate charge and low total power loss of the application system containing device and peripheral parts such as anode reactor and snubber capacitance. In this paper we designed GCT thyristor devices, and analyzed static and dynamic characteristics of GCT thyristor depending on the minority carrier lifetime, n-base thickness and doping concentration of n-base region, respectively. Especially, turn-on and turn-off characteristics are very important characteristics for GCT thyristor devices. So, we considered above characteristic for design and analysis of GCT devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.374-377
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• 2003

In this paper, turn on characteristics of (Punch-Through Insulated Gate Bipolar Transistor) PT-IGBT has been studied. Based on the transient power loss, turn on charges first base to collector capacitance. Furthermore we present the charge variation in the base including n+ buffer layer to express the transient turn-on characteristics of the device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.1-4
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• 1996

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.917-918
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• 2006

In this paper, a novel new pulse power generatorbased on IGBT stacks is proposed for pulse power application. Proposed scheme consists of series connected 9power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is importantfor series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used.

• Journal of Information Display
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• v.6 no.4
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• pp.6-10
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• 2005

The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.

• Transactions on Electrical and Electronic Materials
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• v.15 no.1
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• pp.37-40
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• 2014

A novel memory is reported, in which $Ge_2Sb_2Te_5$ (GST) has been used as a floating gate. The threshold voltage was shifted due to the phase transition of the GST layer, and the hysteretic behavior is opposite to that arising from charge trapping. Finite Element Modeling (FEM) was adapted, and a new simulation program was developed using c-interpreter, in order to analyze the small shift of threshold voltage. The results show that GST undergoes a partial phase transformation during the process of RESET or SET operation. A large $V_{TH}$ shift was observed when the thickness of the GST layer was scaled down from 50 nm to 25 nm. The novel 1 transistor PCM (1TPCM) can achieve a faster write time, maintaining a smaller cell size.

• Journal of Power Electronics
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• v.17 no.3
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• pp.621-631
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• 2017

A KY converter integrated with a conventional synchronously rectified (SR) boost converter and a coupled inductor is presented in this paper. This improved KY converter has the following advantages: 1) the two converters use common switches; 2) the voltage gain of the KY converter can be improved due to the integration of a boost converter and a coupled inductor; 3) the leakage inductance of the coupled inductor is utilized to achieve zero voltage switching (ZVS); 4) the current stress on the charge pump capacitors and the decreasing rate of the diode current can be limited due to the use of the coupled inductor; and 5) the output current is non-pulsating. Moreover, the active switches are driven by using one half-bridge gate driver. Thus, no isolated driver is needed. Finally, the operating principle and analysis of the proposed converter are given to verify the effectiveness of the proposed converter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.405-408
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• 2004

In this work, Analytical model for voltage and current characteristics of NPT(Non-PunchThrough) IGBT(Insulated Gate Bipolar Transistor) was represented. voltage and current characteristics models were based on prediction on power loss of NPT IGBT during transient condition. For Analytical current model, excess carrier concentration and accumulated charge in active base width was analyzed with time variance. Analytical models were simulated by varying lifetime of excess minority carrier.