• Proceedings of the KIEE Conference
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• 2008.11a
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• pp.429-431
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• 2008

기후변화협약 체결 당시 개발도상국으로 분류되어 있던 우리나라는 현재 온실가스 감축의무를 부담하지 않고 있으나, 우리나라의 CO2 배출량 및 배출량 증가율을 고려해 볼 때, 제2차 공약기간(2012년$\sim$2016년) 동안의 온실가스 감축의무 부담이 예견되고 있다. 온실가스 감축의무를 이행하기 위하여 정부는 2012년부터 RPS(Renewable Portfolio Standard) 제도를 도입을 고려하고 있다. 신재생에너지전원의 비중을 설비용량의 5%(발전량의 7%)까지 확대를 예상하여, 본 연구에서는 RPS 제도를 도입을 고려할 때 전원구성의 변화를 GATE -PRO(Generation And Transmission Expansion PROgram)모형을 이용하여 알아본 후, 이로 인하여 전기를 사용하는 용도에 따라 6가지 종별로 구분하는 현행 전기요금체계에 미치는 영향에 대하여 알아보고자 한다.

• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.43-46
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• 2007

In this paper, a novel new pulse power generator based on IGBT stacks is proposed for pulse power application. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is important for series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used. Proposed scheme has lots of advantages such as long lifecyle, compact size, flat topped pulse forming, small weight, protection for arc, high efficiency and flexibility to generate various kinds of pulse output.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1023_1024
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• 2009

In this paper, a novel 10kV, 50A, 50kHz pulsed power supply based on IGBT stacks is proposed. Proposed scheme consists of series connected 12 IGBT to generate maximum 10kV output pulse and 10kW full bridge phase-shifted zero voltage switching converter to charge DC capacitor voltage. Each IGBTs are sustain the 830V of capacitor voltage at turn off interval. By turn on the each IGBT for the same time it gives the path for the series connection of charged capacitor. From above turn on and off procedure, high voltage repetitive pulse is applied to the load. The synchronization of gating signal is important of series operation of IGBTs. For gating signal synchronization, specially designed gate power circuit using full bridge inverter and pulse transformer is developed to generate IGBT gating signal.

• Applied Science and Convergence Technology
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• v.24 no.1
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• pp.16-21
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• 2015

The characteristics of an atmospheric pressure plasma jet (APPJ) in He discharge are measured with electrical and optical diagnostics methods. The discharge phenomenon in one cycle of the APPJ was diagnosed using intensified charge coupled device (ICCD) imaging. The gate mode images show that the propagation of plasma bullets happens only when the applied voltage on the inner conductor is positive. Moreover, the Schlieren image of the plasma jet shows that the laminar flow is changed into a turbulent flow when the plasma jet is turned on, especially when the gas flow rate increases.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.1-4
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• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.1-4
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• 1998

In this paper, we have studied a variation of I-V characteristics, and time-dependent dielectric breakdown(TDDB) of thin layer NO and ONO film depending on nitridation and reoxidation time, respectively, and measured a variation of leakage current and charge-to-breakdown(Q$\_$bd/) of optimized NO and ONO film depending on ambient temperature, and then compared with the properties of conventional SiO$_2$. From the results, we find that these NO and ONO thin films are strongly influenced by process time and the optimized ONO film shows superior dielectric characteristics, and Q$\_$bd/ performance over the NO film and SiO$_2$, while maintaining a similar electric field dependence compared with NO layer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.709-715
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• 1990

SiO2 films were nitrided by tungsten-halogen heated rapid thermal annealing in ammonia gas at temperatures of 900-1100\ulcorner for 15-180sec. The nitroxide films were analyzed using Auger electron spectroscopy. MIS caapcitors were fabricated using these films as gate insulators. I-V and C-V characteristics of MIS capacitors were investigated. The AES depth profiles of nitroxide film show that the nitrogen rich layer is, at the early stage of nitridation, formed at the surface of nitroxide film and near the interface between nitroxide and silicon. Nitridation of SiO2 makes the film have a larger effective average refractive index. The thermal nitridation of SiO2 on silicon causes the flatband voltage shift due to the change of the fixed charge density. It is found that the dominant conduction mechanism in nitroxide is Fowler-Nordheim tunneling. Rapid thermal nitridation of 200\ulcornerSiO2 on silicon results in an improvement in the dielectric breakdown electric field.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.177-180
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• 2001

The quantum effects in the channel of a $\delta$ -doped NMOSFET structures are investigated by solving Schrodinger and Poisson equations self-consistently. According to the scaling of MOSFET structures, electron distributions change by the strong energy quantization. However the presence of a low-doped epitaxial region produces a reduction of the electron effective field for a given charge sheet density and therefore, improves the electron effective mobility. We also focus the quantum-induced threshold voltage shifts, low-field electron effective mobility and gate-to-channel capacitance. The reported results give indications for the fabrication of ultra short MOSFET's.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.