• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.39-46
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• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2217-2222
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• 2011

In this paper, the relationship of potential and charge distribution in channel for double gate(DG) MOSFET has been derived from Poisson's equation using Gaussian function. The relationship of subthreshold swing and oxide thickness has been investigated according to variables of doping distribution using Gaussian function, i.e. projected range and standard projected deviation, The analytical potential distribution model has been derived from Poisson's equation, and subthreshold swing has been obtained from this model for the change of oxide thickness. The subthreshold swing has been defined as the derivative of gate voltage to drain current and is theoretically minimum of 60 mS/dec, and very important factor in digital application. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the relationship of subthreshold swing and oxide thickness have been analyzed according to the shape of doping distribution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.982-988
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• 2012

This paper has presented the relation of scaling theory and threshold voltage of double gate(DG) MOSFET. In the case of conventional MOSFET, current and switching frequency have been analyzed based on scaling theory. To observe the possibility of application of scaling theory for threshold voltage of DGMOSFET, the change of threshold voltage has been observed and analyzed according to scaling theory. The analytical potential distribution of Poisson equation has been used, and this model has been already verified. To solve Poisson equation, charge distribution such as Gaussian function has been used. As a result, it has been observed that threshold voltage is grealty changed according to scaling factor and change rate of threshold voltages is traced for scaling of doping concentration in channel. This paper has explained for the best modified scaling theory reflected the influence of two gates as using weighting factor when scaling theory has been applied for channel length and channel thickness.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.6
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• pp.558-569
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• 2017

In this paper, a 256Kb EEPROM IP aimed at battery applications using a single supply of 1.5V which is embedded into an MCU is designed. In the conventional cross-coupled VPP (boosted voltage) charge pump using a body-potential biasing circuit, cross-coupled PMOS devices of 5V in it can be broken by the junction or gate oxide breakdown due to a high voltage of 8.53V applied to them in exiting the program or erase mode. Since each pumping node is precharged to the input voltage of the pumping stage at the same time that the output node is precharged to VDD in the cross-coupled charge pump, a high voltage of above 5.5V is prevented from being applied to them and thus the breakdown does not occur. Also, all erase, even program, odd program, and all program modes are supported to reduce the times of erasing and programming 256 kilo bits of cells. Furthermore, disturbance test time is also reduced since disturbance is applied to all the 256 kilo bits of EEPROM cells at once in the cell disturb test modes to reduce the cell disturbance testing time. Lastly, a CG driver with a short disable time to meet the cycle time of 40ns in the erase-verify-read mode is newly proposed.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.63.1-63
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• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.8-8
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• 2010

외부전하를 감지할 수 있는 EEPROM 구조를 기반으로 한 센서를 제안하였다. 부유게이트로부터 확장된 큰 면적의 접촉부위 (CCM)는 외부전하를 고정화하도록 설계되었으며, $0.13{\mu}m$ 단일-다결정 CMOS 공정에 적합한 적층의 금속-절연체-금속 (MIM) 제어케이트구조로 구성되었다. N-채널 EEPROM의 CCW 캐패시터 영역에 양의 전압이 인가되면 제어 게이트의 문턱전압이 음의 방향으로 변화하여 드레인 전류는 증가하는 특성을 보였다. 또한 이미 충전된 외부 캐패시터가 CCW의 부유게이트의 금속영역에 직접 연결되면, 외부 캐패시터로부터 유입된 양의 전하는 n-채널 EEPROM의 드레인 전류를 증가시키지만 반면에 음의 전하는 이를 감소시켰다. 외부 전압과 전하에 의해 PMOS의 특성은 NMOS에 비교하여 반대로 나타남이 확인되었다. EEPROM 인버터의 CCW 영역에 외부전하를 연결하면 인버터의 입-출력 특성이 기준 시료에 비해 외부전하의 극성에 따라 변화하였다. 그러므로, EEPROM 인버터는 외부전하를 감지하여 부유게이트에 고정된 전하의 밀도 크기에 따라 출력을 전압으로 표현할 수 있음을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.604-607
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• 2008

In this study, p-channel silicon-oxide-nitride-oxide-silicon (SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are $20{\AA}$ for the tunnel oxide, $14{\AA}$ for the nitride layer, and $49{\AA}$ for the blocking oxide. The fabricated SONGS transistors show low programming voltage, fast erase speed, and relatively good retention and endurance.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.180.2-180.2
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• 2014

Opening a bandgap by forming graphene nanoribbons (GNRs) and tailoring their properties via doping is a promising direction to achieve graphene-based advanced electronic devices. Applying a first-principles computational approach combining density functional theory (DFT) and DFT-based non-equilibrium Green's function (NEGF) calculation, we herein study the structural, electronic, and charge transport properties of boron-nitrogen binary edge doped GNRs and show that it can achieve novel doping effects that are absent for the single B or N doping. For the armchair GNRs, we find that the B-N edge co-doping almost perfectly recovers the conductance of pristine GNRs. For the zigzag GNRs, it is found to support spatially and energetically spin-polarized currents in the absence of magnetic electrodes or external gate fields: The spin-up (spin-down) currents along the B-N undoped edge and in the valence (conduction) band edge region. This may lead to a novel scheme of graphene band engineering and benefit the design of graphene-based spintronic devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.59-69
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• 2002

A semi-analytical model based on exact numerical analysis of the 2DEG channel in pseudo-morphic HEMT (PMHEMT) is presented. The exactness of the model stems from solving both Schrodinger's wave equation and Poisson's equation simultaneously and self-consistently. The analytical modeling of the device terminal characteristics in relation to the charge control model has allowed a best fit with the geometrical and structural parameters of the device. The numerically obtained data for the charge control of the channel are best fitted to analytical expressions which render the problem analytical. The obtained good agreement between experimental and modeled current/voltage characteristics and small signal parameters has confirmed the validity of the model over a wide range of biasing voltages. The model has been used to compare both the performance and characteristics of a PMHEMT with a competetive HEMT. The comparison between the two devices has been made in terms of 2DEG density, transfer characteristics, transconductance, gate capacitance and unity current gain cut-off frequency. The results show that PMHEMT outperforms the conventional HEMT in all considered parameters.