• Title/Summary/Keyword: gate bias voltage

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Fabrication and Characteristics of Long Wavelength Receiver OEIC (장파장 OEIC의 제작 및 특성)

  • 박기성
    • Proceedings of the Optical Society of Korea Conference
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    • 1991.06a
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    • pp.190-193
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    • 1991
  • The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

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Effects of Electrical Stress on Polysilicon TFTs with Hydrogen Passivation (다결정 실리콘 박막 트랜지스터의 수소화에 따른 전기적 스트레스의 영향)

  • Hwang, Seong-Su;Hwang, Han-Uk;Kim, Yong-Sang
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.5
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    • pp.367-372
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    • 1999
  • We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

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Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

  • Kim, Yu-Mi;Jeong, Kwang-Seok;Yun, Ho-Jin;Yang, Seung-Dong;Lee, Sang-Youl;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • v.13 no.1
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    • pp.47-49
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    • 2012
  • In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

Threshold Voltage Roll-off for Bottom Gate Voltage of Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET의 하단게이트 전압에 따른 문턱전압이동현상)

  • Jung, Hakkee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.05a
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    • pp.741-744
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    • 2014
  • This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

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Development of the 120kV/70A High Voltage Switching Circuit with MOSFETs Operated by Simple Gate Drive Unit (120kV/70A MOSFETs Switch의 구동회로 개발)

  • 송인호;최창호
    • The Transactions of the Korean Institute of Power Electronics
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    • v.8 no.1
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    • pp.24-29
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    • 2003
  • A 120kV/70A high voltage switch has been installed at Korea Atomic Energy Research Institute(KAERI) in Taejon to supply power with Korea Superconducting Tokamak Advanced Research(KSTAR) Neutral Beam Injection(NBI) system. NBI system requires fast cutoff of the flower supply voltage for protection of the grid when arc detected and fast turn-on the voltage for sustaining the beam current. Therefore the high voltage switch and arc current detection circuit are important part of the NBI power supply. There are much need for high voltage solid state switches in NBI system and a broad area of applications. This switch consisted of 100 series connected MOSFETs and adopted the proposed simple and reliable gate drive circuit without bias supply. Various results taken during the commissioning phase with a 100kW resistive load and NBI source arc shown. This paper presents the detailed design of 120kV/70A high voltage MOSFETs switch and simple gate drive circuit. Problems with the high voltage switch and gate driver during thefabrication and test and solutions are also presented.

A novel integrated a-Si:H gate driver

  • Lee, Jung-Woo;Hong, Hyun-Seok;Lee, Eung-Sang;Lee, Jung-Young;Yi, Jun-Shin;Bae, Byung-Seong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1176-1178
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    • 2007
  • A novel integrated a-Si:H gate driver with high reliability has been designed and simulated. Since the a-Si:H TFT is easily degraded by gate bias stress, we should optimize the circuit considering the threshold voltage shift. The conventional circuit shows voltage drop at the input stage by threshold voltage of the TFT, however, the proposed circuit dose not shows voltage drop and keeps constant regardless of threshold voltage shift of the TFT.

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Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor (Cooper pair transistor에서 gate voltage에 의한 임계전류의 진동)

  • Song, W.;Chong, Y.;Kim, N.
    • Progress in Superconductivity
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    • v.11 no.2
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    • pp.158-161
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    • 2010
  • We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

Analysis of Failure in Miniature X-ray Tubes with Gated Carbon Nanotube Field Emitters

  • Kang, Jun-Tae;Kim, Jae-Woo;Jeong, Jin-Woo;Choi, Sungyoul;Choi, Jeongyong;Ahn, Seungjoon;Song, Yoon-Ho
    • ETRI Journal
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    • v.35 no.6
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    • pp.1164-1167
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    • 2013
  • We correlate the failure in miniature X-ray tubes with the field emission gate leakage current of gated carbon nanotube emitters. The miniature X-ray tube, even with a small gate leakage current, exhibits an induced voltage on the gate electrode by the anode bias voltage, resulting in a very unstable operation and finally a failure. The induced gate voltage is apparently caused by charging at the insulating spacer of the miniature X-ray tube through the gate leakage current of the field emission. The gate leakage current could be a criterion for the successful fabrication of miniature X-ray tubes.

The Characteristics of MOSFET with Reoxidized Nitrided Oxide Gate Dielectrics (재산화된 질화 산화막을 게이트 절연막으로 사용한 MOSFET의 특성)

  • 양광선;박훈수;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.9
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    • pp.736-742
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    • 1991
  • N$^{+}$poly gate NMOSFETs and p$^{+}$ poly gate (surface type) PMOSFETs with three different gate oxides(SiO2, NO, and ONO) were fabricated. The rapid thermal nitridation and reoxidation techniques have been applied to gate oxide formation. The current drivability of the ONO NMOSFET shows larger values than that of the SiO2 NMOSFET. The snap-back occurs at a lower drain voltage for SiO$_2$ cases for ONO NMOSFET. Under the maximum substrate current bias conditions, hot-carrier effects inducting threshold voltage shift and transconductance degradation were investigated. The results indicate that ONO films exhibit less degradation in terms of threshold voltage shift. It was confirmed that the ONO samples achieve good improvement of hot-carrier immunity. In a SiO$_2$ SC-PMOSFET, with significant boron penetration, it becomes a depletion type (normally-on). But ONO films show excellent impurity barrier properties to boron penetration from the gate.

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Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • Journal of Information Display
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    • v.7 no.3
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    • pp.27-30
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    • 2006
  • This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.