• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.953-956
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• 2009

We have investigated the effect of light on amorphous silicon thin film transistors based photo-sensor applications. We have analyzed the instability caused by electrical gate bias stresses under the light illumination and the effect of photo-induced quasi-annealing on the instability. Threshold voltage ($V_{TH}$) under the negative gate bias stress with light illumination was more decreased than that under the negative gate bias stress without light illumination even though $V_{TH}$ caused by the light-induced stress without negative gate bias was shifted positively. These results are because the increase of carrier density in a channel region caused by the light illumination has the enhanced effect on the instability caused by negative gate bias stress. The prolonged light illumination led to the recovery of shifted VTH caused by negative gate bias stress under the light illumination due to the recombination of trapped hole charges.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• 전기전자학회논문지
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• 제22권1호
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• pp.205-208
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• 2018

본 연구에서는 상시불통형 p-AlGaN-게이트 질화갈륨(GaN) 이종접합 트랜지스터의 신뢰성 평가를 위한 가속열화 시험 조건을 수립하기 위해 게이트 전압 열화 시험을 진행하였다. 상시불통형 트랜지스터의 동작 조건을 고려하여 기존 상시도통형 쇼트키-게이트 소자평가에 사용되는 게이트 역전압 시험과 더불어 순전압 시험을 수행하여 열화특성을 분석하였다. 기존 상시도통형 소자와 달리 상시불통형 소자에서는 게이트 역전압 시험에 의한 열화는 관찰되지 않은 반면, 게이트 순전압 시험에서 심한 열화가 관찰되었다. 상시불통형 질화갈륨 전력 반도체 소자의 신뢰성 평가에 게이트 순전압 열화 시험이 포함되어야 함을 제안한다.

• Transactions on Electrical and Electronic Materials
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• 제13권1호
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• pp.47-49
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• 2012

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.368-368
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• 2010

Using TFTs crystallized by MICC and ELA, electron mobility and threshold voltage were measured according to various substrate temperature from $-40^{\circ}C$ to $100^{\circ}C$. Basic curve, $V_G-I_D$, is also measured under various stress time from 1s to 10000s. Consequently, due to the passivation effect and number of grains, mobility of MICC is varied in the range of -8% ~ 7.6%, while that of ELA is varied from -11.04% ~ 13.25%. Also, since $V_G-I_D$ curve is dominantly affected by grain size, active layer interface, the graph remained steady under the various gate bias stress time from 1s to 10000s. This proves the point that MICC can be alternative technic to ELA.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.769-772
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• 2014

비정질 InGaZnO 박막트랜지스터의 Gate Overlap 길이에 따른 NBS(Negative Bias Stress) 및 hot carrier 스트레스 후 시간별 문턱전압의 변화에 의한 소자신뢰도를 분석하였다. 측정에 사용된 소자는 비정질 InGaZnO TFT이며 채널 폭 $W=104{\mu}m$, 게이트 길이 $L=10{\mu}m$이며 Gate Overlap 길이는 $0,1,2,3{\mu}m$를 사용하였다. 소자 신뢰도는 전류-전압을 측정하여 분석하였다. 측정 결과, hot carrier 스트레스 후 Gate Overlap 길이가 증가할수록 문턱전압의 변화가 증가하였다. 또한, NBS 후에는 Gate Overlap 길이가 증가할수록 문턱전압의 변화가 감소하였고 장시간 스트레스 후에 hump가 발생하였다.

• Journal of Information Display
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• 제13권1호
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• pp.51-54
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• 2012

In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.