• Transactions of the Korean Society of Automotive Engineers
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• v.25 no.1
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• pp.92-102
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• 2017

For an automotive surveillance radar system, fast-chirp train based FMCW (Frequency Modulated Continuous Wave) radar is a very effective method, because clutter and moving targets are easily separated in a 2D range-velocity map. However, pedestrians with low echo signals may be masked by strong clutter in actual field. To address this problem, we proposed in the previous work a clutter cancellation and moving target indication algorithm using the coherent phase method. In the present paper, we initially composed the test set-up using a 24 GHz FMCW transceiver and a real-time data logging board in order to verify this algorithm. Next, we created two indoor test environments consisting of moving human and stationary targets. It was found that pedestrians and strong clutter could be effectively separated when the proposed method is used. We also designed and implemented these algorithms in FPGA (Field Programmable Gate Array) in order to analyze the hardware and time complexities. The results demonstrated that the complexity overhead was nearly zero compared to when the typical method was used.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.11
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• pp.115-120
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• 2005

This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• Smart Structures and Systems
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• v.11 no.3
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• pp.261-282
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• 2013

Structural health monitoring (SHM) is an application area of Wireless Sensor Networks (WSNs) which usually needs high data communication rate to transfer a large amount of monitoring data. Traditional sink node can only process data from one communication channel at the same time because of the single radio chip structure. The sink node constitutes a bottleneck for constructing a high data rate SHM application giving rise to a long data transfer time. Multi-channel communication has been proved to be an efficient method to improve the data throughput by enabling parallel transmissions among different frequency channels. This paper proposes an 8-radio integrated sink node design method based on Field Programmable Gate Array (FPGA) and the time synchronization mechanism for the multi-channel network based on the proposed sink node. Three experiments have been performed to evaluate the data transfer ability of the developed multi-radio sink node and the performance of the time synchronization mechanism. A high data throughput of 1020Kbps of the developed sink node has been proved by experiments using IEEE.805.15.4.

• Journal of Advanced Navigation Technology
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• v.20 no.5
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• pp.453-461
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• 2016

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.134-141
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• 2020

Telemetry system is a communication system that measures and transmits various signals in the aircraft to the ground for collecting and monitoring flight data during the development of unmanned air vehicle and satellite launch vehicles. With the recent development of wireless communication technology, it is becoming important to apply encryption of telemetry system to prepare with security threats that may occur during flight data transmission. In this paper, we suggested and implemented the application method of ARIA-256, Korean standard encryption algorithm, to apply encryption to telemetry system. In consideration of the block error propagation and the telemetry frame characteristics, frame is encrypted using the CTR mode and can apply the Reed-solomon codes recommended by CCSDS. ARIA algorithm and cipher frame are implemented in FPGA, and simulation and hardware verification system confirmed continuous frames encryption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.601-606
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• 2017

SRAM-based FPGAs mainly used to develop and implement high-performance circuits have SRAM-type configuration memory. Soft errors in memory devices are the main threat from a reliability point of view. Soft errors occurring in the configuration memory of FPGAs cause FPGAs to malfunction. SEM(Soft Error Mitigation) Controllers offered by Xilinx can mitigate the influence of soft errors in configuration memory. SEM Controllers use ECC(Error Correction Code) and CRC(Cyclic Redundancy Code) which are placed around the configuration memory to detect and correct the errors. The correction is done through a partial reconfiguration process. This paper presents the availability analysis of SRAM-based FPGAs against soft errors under the protection of SEM Controllers. Availability functions were derived and compared according to the correction capability of SEM Controllers of several different families of FPGAs. The result may help select an SRAM-based FPGA part and estimate the availability of FPGAs running in an environment where soft errors occur.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1417-1422
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• 2005

Among the sensors mainly used for displacement measurement, there are a linear CCD(Charge Coupled Device) and a PSD(Position Sensitive Detector) as a non-contact type. Their structures are different very much, which means that the signal processing of both sensors should be applied in the different ways. Most of the displacement measurement systems to get the 3-D shape profile of an object using a linear CCD are a computer-based system. It means that all of algorithms and mathematical operations are performed through a computer program to measure the displacement. However, in this paper, the developed system has microprocessor and other digital components that make the system measure the displacement of an object without a computer. The thing different from the previous system is that AVR microprocessor and FPGA(Field Programmable Gate Array) technology, and a comparator is used to play the role of an A/D(Analog to Digital) converter. Furthermore, an ATC(Automatic Threshold Control) algorithm is applied to find the highest pixel data that has the real displacement information. According to the size of the light circle incident on the surface of the CCD, the threshold value to remove the noise and useless data is changed by the operation of AVR microprocessor. The total system consists of FPGA, AVR microprocessor, and the comparator. The developed system has the improvement and shows the better performance than the system not using the ATC algorithm for displacement measurement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.65-77
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• 2000

We propose a new formulation by quadratic boolean programming to partition circuits for FPGA based reconfigurable circuit boards, in which the routing topology among IC chips are predetermined. The formulation is to minimize the sum of the wire length by considering the nets passing through IC chips for the interconnections between chips which are not adjacent, in addition to the constraints considered by the previous partition methods. We also describe a heuristic method, which consist of module assignment method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the given constraints are all satisfied for all the benchmark circuits tested. The pin utilization are reduced for the most of the circuits and the total wire length of the routed nets are improved up to 34.7% compared to the previous method.

• Journal of Ocean Engineering and Technology
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• v.28 no.2
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• pp.160-166
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• 2014

Because of industrial development, industrial facilities are becoming more complex and diversified. Plant industries are focused on productivity improvement, cost reduction, and product uniformity by simplifying production processes using automated control. Furthermore, plant industries require higher pressures and temperatures to improve energy efficiency. For this reason, the valves used in plants are operated under harsh conditions. Globe valves and gate valves are mainly used for high pressure these days. However, these valves have various problems, including low maintainability and high cost, due to structural problems. Therefore, butterfly and ball valve applications are increasing in industrial plants. This paper suggests a quadruple-offset butterfly valve that is applicable to bi-direction use, and the principle design parameters are suggested. The selected design parameters are an eccentric flange center line and shaft centerline(Offset 1), an eccentric seat centerline and disc shaft centerline(Offset 2), the angle between the flange centerline and seat wedge angle(Offset 3), the angle between the vertical direction of the disc shaft centerline and seat centerline(Offset 4), and the seat engagement angle. To analyze the interaction effect of the design parameters, ANOM and ANOVA were performed with an orthogonal array. The parameters were found to have effects in the following order: Offset 2, Offset 1, engagement angle, Offset 3, and Offset 4. The interaction between the parameters was insignificant.