• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.04a
• /
• pp.39-40
• /
• 2008

We have examined post-annealing and passivation for the transparent bottom gate IGZO TFT having an inverse co-planar structure. The oxygen-vacuum two step annealing enhanced the field effect mobility up to 18 $cm^2$/Vsandthesub-threshold swing down to 0.2V/dec. However, the hysterysis and the bias stability problems could not be solved just by post-annealing. Thus, we have passivated the bottom gate IGZO TFTs with organic and inorganic materials. $Ga_2O_3$, $Al_2O_3$, $SiO_2$ and some polymer materials were effective materials for passivations. The hysterysis and the stability of the TFTs were remarkably improved by the passivations. We have manufactured the AMOLED panel with the transparent bottom gate IGZO TFT array successfully.

• The Bulletin of The Korean Astronomical Society
• /
• v.40 no.2
• /
• pp.44.1-44.1
• /
• 2015

We set up a project to make spectrometers for single dish observations of the Korean VLBI Network (KVN), a new future multi-beam receiver of the ASTE (Atacama Submillimeter Telescope Experiment), and the total power (TP) antennas of the Atacama Large Millimeter/submillimeter Array (ALMA). Traditionally, spectrometers based on ASIC (Application-Specific Integrated circuit) and FPGA (Field-Programmable Gate Array) have been used in radio astronomy. It is, however, that a Graphics Processing Unit (GPU) technology is now viable for spectrometers due to the rapid improvement of its performance. A high-resolution spectrometer should have the following functions: poly-phase filter, data-bit conversion, fast Fourier transform, and complex multiplication. We wrote a program based on CUDA (Compute Unified Device Architecture) for a GPU spectrometer. We measured its performance using two GPU cards, Titan X and K40m, from NVIDIA. A non-optimized GPU code can process a data stream of around 2 GHz bandwidth, which is enough for the KVN spectrometer and promising for the ASTE and ALMA TP spectrometers.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.50 no.8
• /
• pp.409-413
• /
• 2001

In the electron-gun of CRT, the Mo-tip FEA was employed as cold cathode in order to replace the conventional thermal cathode. The Mo-tip FEA was designed and fabricated according to CRT specification and mounted on the electron-gun. It was known that fabricated cold cathode electron-gun showed better performance in terms of maximum emission current and switch-on time when compared with the ones of thermal cathode electron-gun, but some geometrical structures in the inside of electron-gun must be changed to reduce the gate leakage current. Finally, the potential applicability was guaranteed by means of operating the 19 inch-sized LG-color CRT using the fabricated cold cathode electron-gun.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.309-312
• /
• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.369-372
• /
• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.533-536
• /
• 1988

For CMOS, this paper propose a new global routing algorithm in which macrocells and I/O padcells can be treated. Not only predefined feedthrough in base array, but also some polysilicon line which are not assigned as inputs are used to prevent the overflow of nets passing through the row. The signal nets are assigned on their feedthrough by the maze router. By treating macrocells and I/O padcell, the routing from internal to I/O cell can be done automatically and a kind of is constraints in design process can be reduced.

• Proceedings of the KIEE Conference
• /
• 2000.11c
• /
• pp.452-454
• /
• 2000

In recent years, the Thin Film Transistor Liquid Crystal Display (TFT-LCD) is used in a variety of products as an interfacing device between human and them. Since TFT-LCDs have trend toward larger Panel sizes and higher spatial and/or gray-scale resolution, pixel charging characteristic is very important for the large panel size and high resolution TFT-LCD pixel characteristics. In this paper, both data line precharging method and line time extension (LiTEX) method is applied to Pixel Design Array Simulation Tool (PDAST) and the pixel charging characteristics of TFT-LCD array were simulated, which were compared with the results calculated by both PDAST In which the conventional device model of a-Si TFTs and gate step method is implemented.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.52 no.12
• /
• pp.708-716
• /
• 2003

The surface EMG signal detected from voluntarily activated muscles can be used as a control signal for functional electrical stimulation. To use the voluntary EMG signal, it is necessary to eliminate the muscle response evoked by the electrical stimulation and enable to process the algorithm in real time. In this paper, we propose the Gram-Schmidt(GS) algorithm and implement it in FPGA(field programmable gate array). GS algorithm is efficient to eliminate periodic signals like muscle response, and is more stable and suitable to FPGA implementations than the conventional least-square approach, due to the systolic array structure.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.50 no.2
• /
• pp.87-92
• /
• 2001

This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is $2{\times}2$, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2${\mu}m$ double poly CMOS parameters of MOSIS fabrication process.

• Proceedings of the KIEE Conference
• /
• 1999.07d
• /
• pp.1750-1752
• /
• 1999

An active-matrix liquid crystal display (LCD) using thin film transistors (TFTs) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the sate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed. The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.