• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1631-1633
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• 2008

We demonstrate 4-in QVGA active-matrix electrophoretic display based on ink-jet printed organic transistors on glass substrates. Our TFT array had a bottom-gate, bottom-contact device architecture. The organic semiconductor and gate dielectric were solution processed. The field-effect mobility of the printed devices, calculated in the saturation region, was $0.1{\sim}0.3cm^2/Vs$ at Vg=-20 V.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.481-482
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• 2008

In this paper, the advanced process has been presented to remove the WSix peeling that was made in sub 100nm DRAM SRCAT(Sphere-shaped-Recess-Ch annel-Array Transistor). The source of WSix peeling was proved to be the groove of gate poly film. We have completely solved the problems to adopt the gate-poly CMP (Chemical Mechanical Polishing) process.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.145-151
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• 1989

A new preprocess technique is presented which can improve the routing efficiency in the gate array layout designs. In order to resolve the cycle problem in the detailed routing, we exchange the logically equivalent pins in each channel. The signal nets are divided, and doubly connected signal net components are removed, so that the increase in the number of tracks can be controlled.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.1
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• pp.38-46
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• 2008

Design technology and speciality production technology to manufacture high quality valve are insufficient in Korea. In order to design the experiments using Taguchi method and Variational Technology Also, from verification of the response model with optimized results was confirmed that usefulness and reliance of application Taguchi method and Variational Technology to structural's optimum design using Taguchi method and Variational Technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.213-225
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• 2002

Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.13 no.6
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• pp.73-81
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• 2014

In this paper, multiple gate locations and process conditions under concern are automatically optimized by considering robustness to minimize the injection pressure required to mold an automotive dashboard. Computer simulation-based experiments using orthogonal arrays(OA) and a design-range reduction algorithm are consolidated into an iterative search scheme, which is then used as a tool for the optimization process. The robustness of a design is evaluated using an OA-based simulation of process fluctuations due to noise as well as the signal-to-noise ratio. The optimal design solution for the automotive dashboard shows that the robustness of the injection pressure is significantly improved when compared to the initial design. As a result, both the die clamping force and the pressure distribution in the part cavity are also much improved in terms of their robustness.

• Design & Manufacturing
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• v.10 no.2
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• pp.50-54
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• 2016

In the semiconductor industry the final products were checked for several environments before sell the products. The burning test of memory and chip was implemented in reliability for all of parts. The memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. In this study, injection molding process analysis was executed for 2 and 4 cavities moldings with runner, gate and sprue. The warpage analysis was also implemented for further gate removal process. Through the analyses the total deformations of the moldings were predicted within maximum 0.05mm deformation. Finally in consideration of these results, 2 and 4 cavities molds were designed and made and tested in injection molding process.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.