• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• The Journal of the Korea Contents Association
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• v.18 no.1
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• pp.10-18
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• 2018

This paper presents a method to resynthesize logic of a programmed FPGA from a bitstream file that is a downloaded file for Xilinx FPGA (Field Programmable Gate Array). It focuses on reconfiguring the LUT (Look Up Table) logic. The bitstream data is compared and analyzed considering various situations and various input variables such as composing other logics using the same netlist or synthesizing the same logic at various positions to find a structure of the bitstream. Based on the analyzed bitstream, we construct a truth table of the LUT by implementing various logic for one LUT. The proposed algorithm extracts the logic of the LUT based on the truth table of the generated LUT and the bitstream. The algorithm determines the input and output pins used to implement the logic in the LUT. As a result, we extract a gate level logic from a bitstream file for the targeted Xillinx FPGA.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.7
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• pp.84-90
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• 2022

The purpose of the cover housing component of a car door is to protect the terminals of the plug housing that connects the electric control unit on the door side to the car body. Therefore, for a smooth assembly with the plug housing and to prevent contaminants from penetrating into the gaps that occur after assembly, the warpage of the cover housing should be minimized. In this study, to minimize the warpage of the cover housing, optimization was performed for design factors related to the mold and processes based on the injection molding simulation. These design factors include gate location, gate diameter, injection time, resin temperature, mold temperature, and packing pressure. To optimize the design factors, Taguchi's approach to the design of experiments was adopted. The optimal combination of the design factors and levels that minimize warpage was predicted through L₁₈-orthogonal array experiments and main effects analysis. Moreover, the warpage under the optimal design was estimated by the additive model, and it was confirmed through the simulation experiment that the estimated result was quite consistent with the experimental result. Additionally, it was found that the warpage under the optimal design was significantly improved compared to both the warpage under the initial design and the best warpage among the orthogonal array experimental results, which numerically decreased by 36.9% and 23.4%, respectively.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.11
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• pp.2902-2912
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• 1994

The ultrasonic array sensor system, consisting of one transmitter and fourreceivers instead of the traditional combination of a transmitter and a receiver is proposed in order to identify the location of objects. From the theoretical analysis and the experimental results, it is found that this new array sensor system could derive the information on the position of objects accurately, while the traditional sensor system could provide only the informatioin on the distance to objects. This sensor system is used to develop a sonar-based local mapping algorithm. The local map is used to find the existence of possible gates, through which the mobile robots can pass, and to select the suitable one in order for the robots to reach the goal safely in the presence of obstacles. The performance of the proposed local map algorithm is demonstrated experimentally in a small working area with several obstacles. It is found that the quality of the resulting local map is sufficient for the avoidance of collisions between the robots and obstacles and for the selection of the suitable gate leading to the goal. It is also shown that the global map of the working area could be obtained by integrating several local maps constructed from different locations and that it matches the actual layout of the working area well.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.151-159
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• 2022

In this paper, we implement a digital multi-beamformer using FPGA(Field Programmable Gate Array) which has advantages in parallel and real-time data processing. This is accomplished through the use of not only high-speed data communication but also multiple beam forming, which is currently required by MFR(Multi Function Radar). As a result, the beamformer can process 24 Gbps throughput in real-time and form 5 digital beams at the same time. It is also compared to the results of Matlab simulations. We demonstrate how an implemented beamformer can be used in an MFR system by using a digital array antenna.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.171-175
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• 2006

In this paper, we have developed a retrodirective active array operating in the 2 GHz LS band. The retrodirective array has the property of redirecting any electromagnetic wave back to the incoming direction without any priory informations. The system is integrated with phase conjugators and antenna array. Microwave phase conjugators can be implemented by microwave mixers. In this research, 2-port gate mixers using pHEMT and $1{\times}4$ monopole array have been used to achieve the retrodirectivity. The measured results have been compared with the theoretical prediction, and it has been shown that there exists a reasonable agreement between them. The monopole array can be used easily in many areas for simplicity and cost-effective property, and the retrodirective array developed in this research can be applied directly in the base station facilities for the wireless mobile communications. indoor wireless LAN and RFID transponders.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.9
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• pp.1614-1618
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• 2007

We have demonstrated the experimental results to obtain the immunity of FN (Fowler Nordheim) stress for S-RCAT (Spherical-Recess Cell Array Transistor) which has been employed to meet the requirements of data retention time and propagation delay time for sub-100-nm mobile DRAM (Dynamic Random Access Memory). Despite of the same S-RCAT structure, the immunity of FN stress of S-RCAT depends on the process condition of gate oxidation. The S-RCAT using DPN (decoupled plasma nitridation) process showed the different degradation of device properties after FN stress. This paper gives the mechanism of FN-stress degradation of S-RCAT and introduces the improved process to suppress the FN-stress degradation of mobile DRAM.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09b
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• pp.122-125
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• 2003

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.