• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.678-686
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• 2001

Origins for the transconductance dispersion and the gate leakage current in a GaAs metal semiconductor field effect transistor were found using capacitance deep-level transient spectroscopy (DLTS) measurements. In DLTS spectra, we observed two surface states with thermal activation energies of 0.65 $\times$ 0.07 eV and 0.88 $\times$ 0.04 eV and an electron trap EL2 with thermal activation energy of 0.84 $\times$ 0.01 eV. Transconductance was decreased in the frequency range of 5.5 Hz ~ 300 Hz. The transition frequency shifted to higher frequencies with the increase of temperature and the activation energy for the change of the transition frequency was determined to be 0.66 $\times$ 0.02 eV. From the measurements of the gate leakage current as a function of the device temperature, the forward and reverse currents are coincident with each other below gate voltages lower than 0.15 V, namely Ohmic behavior between gate and source/drain electrodes. The activation energy for the conductance of electrons on the surface of MESFET was 0.63 $\times$ 0.01 eV. Comparing activation energies obtained by different measurements, we found surface states H1 caused the transconductance dispersion and the fate leakage current.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.164-169
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• 2008

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.20-23
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• 2000

We have investigated a process for the preparation of high-quality tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$) via the N $H_3$ annealing of 7$_{a2}$ $O_{5}$, for use in gate dielectric applications. Compared with tantalum oxide (7$_{a2}$ $O_{5}$), a significant improvement in the dielectric constant was obtained by the N $H_3$ treatment. In addition, light reoxidation in a wet ambient at 45$0^{\circ}C$ resulted in a significantly reduced leakage current. We confirmed nitrogen incorporation in the tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$ by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness as thin as 1.6nm and a leakage current of less than 10mA/$\textrm{cm}^2$ at 1.5V..5V..5V..5V..5V..5V.

• ETRI Journal
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• v.38 no.4
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.71-74
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• 1998

In this Paper, we investigate the electrical properties of ultra-thin(70${\AA}$) nitrided(NO) and reoxidized nitrided oxide(ONO) film that ale considered to be premising candidates for replacing conventional silicon dioxide film in ULSI level integration. we studied I$\sub$g/-V$\sub$g/ characteristics to know the effect of nitridation and reoxidation on the current conduction, leakage current time-dependent dielectric breakdown(TDDB) to evaluate charge-to-breakdown(Q$\sub$bd/), and the effect of stress temperature(25, 50, 75, 100$^{\circ}C$) and compared to those with thermal gate oxide(SiO$_2$) of identical thickness. From the measurement results, we find that reoxidized nitrided oxide(ONO) film shows superior dielectric characteristics, leakage current, and breakdown-to-charge(Qbd) performance over the NO film, while maintaining a similar electric field dependence compared to NO layer. Besides, ONO film has strong resistance against variation in temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.331-331
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• 2009

Hafnium oxide ($HfO_2$) attracted by one of the potential candidates for the replacement of si-based oxides. For applications of the high-k gate dielectric material, high thermodynamic stability and low interface-trap density are required. Furthermore, the amorphous film structure would be more effective to reduce the leakage current. To search the gate oxide materials, metal-insulator-metal (MIM) capacitors was fabricated by pulsed laser deposition (PLD) on indium tin oxide (ITO) coated glass with different oxygen pressures (30 and 50 mTorr) at room temperature, and they were deposited by Au/Ti metal as the top electrode patterned by conventional photolithography with an area of $3.14\times10^{-4}\;cm^2$. The results of XRD patterns indicate that all films have amorphous phase. Field emission scanning electron microscopy (FE-SEM) images show that the thickness of the $HfO_2$ films is typical 50 nm, and the grain size of the $HfO_2$ films increases as the oxygen pressure increases. The capacitance and leakage current of films were measured by a Agilent 4284A LCR meter and Keithley 4200 semiconductor parameter analyzer, respectively. Capacitance-voltage characteristics show that the capacitance at 1 MHz are 150 and 58 nF, and leakage current density of films indicate $7.8\times10^{-4}$ and $1.6\times10^{-3}\;A/cm^2$ grown at 30 and 50 mTorr, respectively. The optical properties of the $HfO_2$ films were demonstrated by UV-VIS spectrophotometer (Scinco, S-3100) having the wavelength from 190 to 900 nm. Because films show high transmittance (around 85 %), they are suitable as transparent devices.

• Journal of the Semiconductor & Display Technology
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• v.6 no.4
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• pp.69-73
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• 2007

The MIM(metal-insulator-metal) capacitors with the Al/PMMA/ITO/Glass structures were manufactured according to various PMMA concentration of 1, 2, 4, 6, 8 wt%. The lowest leakage current and the largest capacitance were found to be 2.3 pA and 1.2 nF, respectively, for the device with 2 wt% PMMA concentration. The measured capacitance of the devices was almost same values with the calculated one. The optimum film thickness was obtained at the value of 48 nm, showing that the capacitance and leakage current were 1.92 nF, 0.3 pA at 2 wt%, respectively. From this experiment, the PMMA gate insulator films can be applicable to the organic thin film transistors.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.27-31
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• 2007

The cpapcitors with MIM(metal-insulator-metal) structures using PVP gate insulation films were prepared for the application of flexible organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as a solute and PGMEA(propylene glycol monomethyl ether acetate) as a solvent. The cross-linked PVP insulation films were also prepared by addition of poly(melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross- linked PVP films was found to be about 1.3 nA on Al/PES(polyethersulfone) substrate, whereas, on ITO/ glass substrate was about 27.5 nA indicating improvement of the leakage current at Al/PES substrates. Also, the capacitances of all prepared samples on ITO/glass and Al/PES substrates w ere ranged from 1.0 to $1.2nF/cm^2$, showing very similar result with the calculated capacitance values.