• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.97-100
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• 2001

This paper presents the characteristics of Ta-N thin-film strain gauges as high-temperature strain gauges, which were deposited on Si substrate by DC reactive magnetron sputtering in an argon-nitrogen atmosphere(Ar-(4~16%)$N_2$). These films were annealed for 1 hour in $2{\times}10^{-6}$ Torr vaccum furnace range $500\sim1000^{\circ}C$. The optimized conditions of Ta-N thin-film strain gauges were annealing condition($900^{\circ}C$, 1 hr.) in 8% $N_2$ gas flow ratio deposition atmosphere. Under optimum conditions, the Ta-N thin-films for strain gauges is obtained a high resistivity, $\rho=768.93$ ${\mu}{\Omega}cm$, a low temperature coefficient of resistance, TCR=-84 ppm/$^{\circ}C$ and a high temporal stability with a good longitudinal gauge factor, GF=4.12.

• Journal of Surface Science and Engineering
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• v.43 no.1
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.199-200
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• 2006

PM recent developments focus on increasing this technology's competitiveness when compared to wrought materials. Warm compaction allows the replacement of a double press double sinter process with a single warm press and sintering step, thus allowing cost and time savings. Moreover there are added benefits to consider such as reducing work in process and lessening part's logistics cost. This paper presents a successful industrial trial to replace a double press-double sinter process with a warm die compaction and sintering process. The part chosen was a high performance gear containing 0,9% wt. carbon. Sintering was conducted in a belt furnace at $1120^{\circ}C$ in a nitrogen rich atmosphere with rapid cooling process in order to obtain a quasi fully martensitic structure with a minimum of 700HV0,1 and 450HV10 after annealing. The balance between properties and cost is favoured by the use of a singular lubricant developed in a Eureka frame project together with POMETON S.A. and die warm compaction. Warm compaction is only needed to be effective on the gear teeth, in order to achieve the required properties. Therefore only the die is actually heated. This simplified system avoids flow rate problems typically involved when using more elaborate warm compaction equipments.

• Journal of Surface Science and Engineering
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• v.34 no.1
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• pp.33-38
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• 2001

10cm-diameter Si(100)∥$1.3\mu\textrm{m}$-X$1.3_2$X$1.3\mu\textrm{m}$-$SiO_2$∥Si(100) afers were prepared using a fast linear annealing (FLA) equipment. 1.3$\mu\textrm{m}$-thick $SiO_2$ films were grown by dry oxidation process. After cleaning and premating the wafers in a class 100 clean room, they were heat treated using with the FLA and conventional electric furnace. Bonded area and bond strength of wafer pairs were measured using a infrared (IR) camera and razor blade crack opening method, respectively. It was confinmed that the bonded area by FLA was around 99% and the bond strength value reached 2172mJ/$\m^2$, which is equivalent to theoritical bond strength. Our result implies that thick $SiO_2$ SOI may be prepared more easily by using $SiO_2$$SiO_2$ bonding interfaces then those of Si/$SiO_2$'s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.16-17
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• 2006

In this paper, Ni-V alloy was studied with different structures and thickness. In case of Ni-V and Ni-V/Co/TiN, low resistive Ni silicide was formed after one step RTP (Rapid Thermal Process) with temperature range from $400^{\circ}C$ to $600^{\circ}C$ for 30sec in vacuum. After furnace annealing with temperatures range from $550^{\circ}C$ to $650^{\circ}C$ for 30min in nitrogen ambient, Ni-V single structure shows the best thermal stability compare with the other ones. To enhance the thermal stability up to 650oC and find the optimal thickness of Ni silicide, different thickness of Ni-V was studied in this work. Stable sheet resistance was obtained through Ni-V single structure with optimal Ni-V thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.637-638
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• 2005

AAO templates were fabricated using a two-step anodization process with pretreatment such as electro polishing and annealing. To reduce process time and get well-aligned pore array, rapid thermal processor by an halogen lamp was employed in vacuum state at $500^{\circ}C$ for various time. The pore array of AAO template annealed at $500^{\circ}C$ for 2 h is comparable to a template annealed in conventional furnace at $500^{\circ}C$ for 30 h. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrierlayer thickness of 25 nm, and the pore depth of $9{\mu}m$. And the pore density can be as high as $2.0\times10^{10}cm^{-2}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.180-181
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• 2006

CdSe single crystal was grown by sublimation method in the two-step vertical electric furnace. This CdSe single crustal had hexagonal structure whose lattice constants of $a_0$ and $c_0$ were measured $4.299\;{\AA}$ and $7.009\;{\AA}$ by extrapolation method, respectively. CdSe single crystal was n-type semiconductor values were measured from Hall data by Van der Pauw method in the room temperature. Mobility tends to increase in proportion to $T^{3/2}$ from 33K to 130K due to impurity scattering. but mobility tends to decrease in proprtion to $T^{-3/2}$ from 130K to 293K due to lattice scattering. CdSe thin film was made by electron beam evaporation technique had also hexagonal structure. The grain size of this thin film was grown to $1{\mu}m$ as a result of annealing in the vapor of Ar or Cd. Annealde CdSe thin film was n-type semiconductor whose carrier density had about $7{\times}10^{12}cm^{-3}$ and its mobility had about $1.6{\times}10^3cm^2/V$ sec at room temperature.

• Korean Journal of Materials Research
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• v.9 no.3
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• pp.229-233
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• 1999

DC마그네트론 스퍼터링 방식으로 $Ti/SiO_2$/Si 구조 위에 Pt(200) 박막을 배향 성장시키기 위해 증착조건(스퍼터링 가스의 종류와 압력, 기판의 온도)과 후속열처리(RTA, Furnace annealing)에 따른 Pt 박막의 전기, 결정학적 특성을 조사하였다. 실험결과, 20mTorr의 Ar+O$_2$(20%)의 혼합가스 분위기에서 기판온도를 $500^{\circ}C$로 유지하여 Pt박막을 증착하고$ 600^{\circ}C$에서 30초간 급속 열처리를 실시한 경우, 90% 이상의 결정 배항도를 갖는 Pt(200) 박막을 제작할 수 있었다. 제작된 Pt(200) 박막은 $30~40\mu$Ω.cm의 낮은 전기저항율과 우수한 열적 안정성을 나타내었으며$ 600^{\circ}C$의 고온에서 장시간 열처리를 실시하여도 전기저항율이나 우선 배향성의 변화, 박막내 미세 결함 및 열적응집현상 등이 발생되지 않았다.

• Korean Journal of Metals and Materials
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• v.46 no.5
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• pp.315-320
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• 2008

The effect of Mn additive on the thermoelectric properties of Fe-Si alloys prepared by a RF inductive furnace was investigated. The electrical conductivity and Seebeck coefficient were measured as a function of temperature under Ar atmosphere to evaluate their applicability to thermoelectric energy conversion. The electrical conductivity of the specimens increased with increasing temperatures showing typical semiconducting behavior. The electrical conductivity of Mn-doped specimens are higher than that of undoped specimens and increased slightly with increasing the amount of Mn additive. This must be due to the difference in carrier concentration and the amount of residual metallic phase ${\varepsilon}$-FeSi(The ${\varepsilon}$-FeSi was detected in spite of 100 h annealing treatment at $830^{\circ}C$). And metallic conduction increased slightly with increasing the amount of Mn additive. On the other hand, Mn-doped specimens showed the lower Seebeck coefficient due to metallic phase. The power factor of Mn-doped specimens are higher than that of undoped specimens and would be affected by the electrical conductivity more than Seebeck coefficient.